Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing
Shogo Katayama; Takayuki Nakatani; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi
IEICE Electronics Express, 10 Jan. 2023

Metallic Ratio Equivalent-Time Sampling and Application to TDC Linearity Calibration
Shuhei Yamamoto; Yuto Sasaki; Yujie Zhao; Anna Kuwana; Kentaroh Katoh; Zheming Zhang; Jianglin Wei; Tri Minh Tran; Shogo Katayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
IEEE Transactions on Device and Materials Reliability, Jun. 2022

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies
Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Jianglin Wei; Haruo Kobayashi; Takayuki Nakatani; Kazumi Hatayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
Journal of Electronic Testing, Feb. 2022

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
Kentaro KATO; Somsak CHOOMCHUAY
IEICE Transactions on Information and Systems, 2017

Time-to-Digital Converter-Based Maximum Delay Sensor for On-Line Timing Error Detection in Logic Block of Very Large Scale Integration Circuits
Kentaroh Katoh; Kazuteru Namba
SENSORS AND MATERIALS, 2015, Refereed

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator
Kentaroh Katoh; Yutaro Kobayashi; Takeshi Chujo; Junshan Wang; Ensi Li; Conbing Li; Haruo Kobayashi
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, Dec. 2014

Analog/mixed-signal circuit design in nano CMOS era
Haruo Kobayashi; Hitoshi Aoki; Kentaroh Katoh; Congbing Li
IEICE Electronics Express, 2014

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, May 2012, Refereed

Area Reduction Techniques for Embedded Delay Measurement Using Signature Registers
加藤 健太郎
鶴岡工業高等専門学校研究紀要,第46号 pp.61～66, Feb. 2012, Refereed

差分によるVLSI回路の遅延測定
TANABE Toru; KATOH Kentaroh; NAMBA Kazuteru; ITO Hideo
The IEICE transactions on information and systems, Apr. 2010

高集積化システムＬＳＩのためのスキャンテスト設計法
加藤 健太郎
千葉大学, Mar. 2009

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Mar. 2009

Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Feb. 2009

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
IPSJ Transactions on System LSI Design Methodology, Aug. 2008

環境との相互作用を用いた自律移動ロボットの識別能力の進化的獲得
加藤 健太郎
名古屋大学, Mar. 1997

Error Correction and Self-Calibration of Analogue- Digital Mixed-Signal Integrated Circuits
Haruo Kobayashi; Kentatoh Katoh
International Summit on Semiconductors, Optoelectronics and Nanostructures (ISSON2024),, May 2024, Refereed

A Fine On-Chip Online Delay Measurement Using a MUX Chain for Failure Prediction and Analysis
Kentaroh Katoh; Toru Nakura; Xiaoqing Wen; Haruo Kobayashi
the 7th International Conference on Technology and Social Science ICTSS 2023, Dec. 2023, Refereed
Lead

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Keno Sato; Takayuki Nakatani; Takeshi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Daisuke Iimori; Misaki Takagi; Yujie, Zhao; Shuhei Yamamoto; Anna Kuwana; Kentaroh Katoh; Kazumi Hatayama; Kobayashi Haruo
IEEE Int. Test Conf., Oct. 2023, to appaear, Oct. 2023, Refereed

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation
Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
7th IEEE Int. Test Conf. in Asia, Shimane, Japan, Oct. 2023, to appear, Sep. 2023, Refereed
Lead

Inductor ESR Compensation for LC Analog Filters
Misaki Takagi; T. Nakatani; S. Katayama; D. Iimori; G. Ogihara; Y. Zhao; S. Yamamoto; Kobayashi
32nd International Workshop on Post-Binary ULSI Systems (ULSIWS) Matsue, Shimane, Japan, May 2023, Refereed

Design Consideration for LC Analog Filters: Inductor ESR Compensation, Mutual Inductance Effect and Variable Center Frequency
Misaki Takagi; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi
8th International Congress on Information and Communication Technology (ICICT 2023), Feb. 2023, Refereed

SAR Time-to-Digital Converter with 1 ps Resolution for LSI Test System
D. Iimori; T. Nakatani; S. Katayama; M. Takagi; Y. Zhao; A. Kuwana; K. Katoh; K. Hatayama; H. Kobayashi; K. Sato; T. Ishida; T. Okamoto; T. Ichikawa
8th International Congress on Information and Communication Technology (ICICT 2023), Feb. 2023, Refereed

Signal Estimation by Prony's Method for Application to ADC Testing
Siwei Li; Anna Kuwana; Yuki Yanadori; Shogo Katayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Takayuki Nakatanii; Kazumi Hatayama; Haruo Kobayashi
Dec. 2022, Refereed

Effect of the Delay Elements Variation on Time-to-Digital Converter Linearity
Zhang Zheming; Anna Kuwana; Shogo Katayama; Shuhei Yamamoto; Kentaroh Katoh; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, Dec. 2022, Refereed

Time-to-Digital Converter Linearity Calibration with Metallic Ratio Sampling
Shuhei Yamamoto; Kentaroh Katoh; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the Joint International Conferences of the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, Dec. 2022, Refereed

A Physical Unclonable Function Using Time-to-Digital Converter
Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the Joint International Conferences of the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, Dec. 2022, Refereed
Lead

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST
Keno Sato; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Kazumi Hatayama; Haruo Kobayashi
2022 IEEE 31st Asian Test Symposium (ATS), Nov. 2022, Refereed

Evaluation of Code Selective Histogram Algorithm For ADC Linearity Test
Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Daisuke Iimori; Yuki Ozawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
2022 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 26 Oct. 2022, Refereed

Challenges for Waveform Sampling and Related Technologies
Haruo Kobayashi; Kentaroh Katoh; Shuhei Yamamoto; Yujie Zhao; Shogo Katayama; Jianglin Wei; Yonglun Yan; Dan Yao; Xueyan Bai; Anna Kuwana
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 25 Oct. 2022, Refereed

Recent Innovation of Waveform Acquisition Methods: Residue Sampling and Metallic Ratio Sampling
Haruo Kobayashi; Anna Kuwana; Shogo Katayama; Shuhei Yamamoto; Yujie Zhao; Kentaroh Katoh; Yonglun Yan; Koji Asami; Masahiro Ishida
11th IEEE International Conference on Communications, Circuits and Systems, May 2022, Refereed

Innovative Practices Track: Innovative Analog Circuit Testing Technologies
Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel Barragan; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
2022 IEEE 40th VLSI Test Symposium (VTS), 25 Apr. 2022, Refereed

Deterministic Path Delay Measurement Using Short Cycle Test Pattern
Kentaro Kato
2017 IEEE 26th Asian Test Symposium (ATS), Nov. 2017, Refereed
Lead

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement
Kentaroh Katoh; Kazuteru Namba
Sixteenth International Symposium on Quality Electronic Design, Mar. 2015, Refereed

An on-chip delay measurement using adjacency testable scan design
Kentaro Kato; Somsak Choomchuay
2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), 2015, Refereed

Acceleration of scan-based on-chip delay measurement using extra latches and multiple asynchronous transfer scan chains
Kentaro Kato; Somsak Choomchuay
2015 7TH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY AND ELECTRICAL ENGINEERING (ICITEE), 2015, Refereed
Lead

A TDC-Based Online Maximum Delay Analyzer
K. Katoh; K. Namba
International Conference of Global Network for Innovative Technology, Dec. 2014, Refereed
Lead

Time-to-digital converter architecture with residue arithmetic and its FPGA implementation
Congbing Li; Kentaroh Katoh; Junshan Wang; Shu Wu; Shaiful Nizam Mohyar; Haruo Kobayashi
2014 International SoC Design Conference (ISOCC), Nov. 2014, Refereed

Experimental verification of timing measurement circuit with self-calibration
Takeshi Chujo; Daiki Hirabayashi; Congbing Li; Yutaro Kobayashi; Junshan Wang; Haruo Kobayashi; Kentaroh Katoh; Sato Koshi
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, Sep. 2014, Refereed

Digital Compensation for Timing Mismatches in Interleaved ADCs
Ru Yi; Minghui Wu; Koji Asami; Haruo Kobayashi; Ramin Khatami; Atsuhiro Katayama; Isao Shimizu; Kentaroh Katoh
2013 22nd Asian Test Symposium, Nov. 2013, Refereed

Fast Scan-based On-Chip Delay Measurement Using Multiple Asynchronous Transfer Scan Chains
加藤 健太郎
IEEE International Test Conference 2013要旨集, Anaheim, U.S. P012, Oct. 2013, Refereed

バウンダリスキャンと組み込み再構成可能ハードウェアを用いたSOCのオンラインインターコネクトテスト法
加藤 健太郎
電子情報通信学会技術報告,DC-2013-14, pp.25～29, Jun. 2013

隣接テスト機構を用いたオンチップ遅延測定法
加藤 健太郎
電子情報通信学会技術報告, DC-2013-8 pp.43-48, Mar. 2013

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators
Kentaroh Katoh; Yuta Doi; Satoshi Ito; Haruo Kobayashi; Ensi Li; Nobukazu Takai; Osamu Kobayashi
2013 22ND ASIAN TEST SYMPOSIUM (ATS), 2013, Refereed

組み込み遅延測定回路を用いた時分割オンチップパス遅延測定のための入力系列データ量削減の１手法
加藤 健太郎
電子情報通信学会技術報告, DC-2012-6 pp.7-13, Jun. 2012

Time-Multiplexed On-Chip Delay Measurement for Dependable High-Speed Digital LSIs
Kentaroh Katoh; Kei Itagaki; Shinichiro Hoshina
1st IEEE Global Conference on Consumer Electronics 2012, GCCE 2012, 2012, Refereed

半導体集積回路及び半導体集積回路の検査方法（再掲）
加藤 健太郎
特願2009-265825,特開2011-113984, Nov. 2011

A Low Area and Short-Time Scan-based Embedded Delay Measurement Using Signature Registers
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, Refereed

A Low Area On-Chip Delay Measurement System Using Embedded Delay Measurement Circuit
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, Refereed

半導体集積回路及び半導体集積回路の検査方法(再掲）
加藤 健太郎
特願2007-233346,特開2009-063518, Nov. 2009

半導体集積回路(再掲）
加藤 健太郎
特願2007-233388,特開2009-063519, Sep. 2009

A Delay Measurement Technique Using Signature Registers
Kentaroh Katoh; Toru Tanabe; Haque Md Zahidul; Kazuteru Namba; Hideo Ito
2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2009, Refereed

Design for Delay Fault Testing of 2-Rail Logic Circuits
加藤 健太郎
Indonessia-Japan Joint Scientific Symposium要旨集 pp.57-62, Sep. 2008, Refereed

遅延故障テスト容易化FF方式の下での2段階テストデータ圧縮法
加藤 健太郎
電子情報通信学会技術報告, DC-2007-25, Nov. 2007

Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability
Abderrahim Doumar; Kentaroh Katoh; Hideo Ito
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), Sep. 2007, Refereed

粗粒度動的再構成可能デバイスのPE部テストのためのDFT
加藤 健太郎
電子情報通信学会技術報告, DC-2006-4, Apr. 2006

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
Kentaroh Katoh; Hideo Ito
ETS 2006: ELEVENTH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS, 2006, Refereed

Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift
K. Katoh; A. Doumar; H. Ito
11th IEEE International On-Line Testing Symposium, 2005, Refereed

動的命令コード符号化を用いたハッキング検出可能車載向けセキュアプロセッサの開発
日本学術振興会, 科学研究費助成事業, 基盤研究(C)
鶴岡工業高等専門学校
01 Apr. 2018 - 31 Mar. 2021

PRAMの書き込み時間削減に適した符号
Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C)
Chiba University
01 Apr. 2015 - 31 Mar. 2018