18 May 2020
ICCCS 2020, Best Presentation Award
International society
Toshinori Sato

24 Apr. 2008
LSI IPデザイン・アワード運営委員会, 第10回LSI IPデザイン・アワード・MeP賞
計算負荷の変動に瞬時適応可能なマルチパフォーマンスプロセッサ, Publisher
山口誠一朗;大山裕一郎;国武勇次;松村忠幸;石飛百合子;山口聖貴;李東勲;舟木敏正;金田裕介;室山真徳;石原亨;佐藤寿倫

17 Oct. 2007
7th International Conferenceon Computer and Information Technology, Excellent Paper Awards
International society
Shingo Watanabe;Akihiro Chiyonobu;Toshinori Sato

23 May 2007
先進的計算基盤システムシンポジウム, 最優秀論文賞
カナリア・フリップフロップを利用する省電力マイクロプロセッサの評価, Japan society
佐藤寿倫
カナリア・フリップフロップを利用する省電力マイクロプロセッサの評価

25 Jul. 2003
情報処理学会, 平成15年度山下記念研究賞
0/1の局所性を利用したデータ値予測機構のハードウエア量削減, Japan society
佐藤寿倫
0/1の局所性を利用したデータ値予測機構のハードウエア量削減

19 May 2000
情報処理学会, 平成11年度論文賞
2ホップアドレス名前替えを用いたロード命令の投機的実行, Official journal
佐藤寿倫
2ホップアドレス名前替えを用いたロード命令の投機的実行

May 2000
日経ＢＰ社, 第2回IPアワード・開発奨励賞
計算機クラスタによるメモリ共有型計算機のためのメモリ/ネットワークインター フェース・ライブラリ
久家裕司;立川純;大濱智弘;田中康一郎;佐藤寿倫;有田五次郎

27 May 1999
International Symposium on High Performance Computing, Distinguished Paper Award
International society
Toshinori Sato
Profile-based Selection of Load Value and Address Predictors

Cost-effective Alternatives for Squarer in Pan-Tompkins Algorithm
Taiki Nagatomo; Toshinori Sato
Proceedings of the 2024 6th International Electronics Communication Conference, 19 Jul. 2024, :31 - 36, Refereed
Last

Unveiling the Significance of Sign Calculation Impact on JPEG Applications
Hiroyuki Hama; Toshinori Sato; Tomoaki Ukezono
2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 02 Jul. 2024, :1 - 6, Refereed
Corresponding

A Light-weight and Tamper-resistant AES Implementation by FPGAs
Yui Koyanagi; Tomoaki Ukezono; Toshinori Sato
2024 IEEE International Symposium on Circuits and Systems (ISCAS), 19 May 2024, 2003:1 - 5, Refereed
Last

Improving Energy Efficiency in Medical Edge Devices for ECG Feature Detection via Approximate Computing
Taiki Nagatomo; Toshinori Sato
2023 IEEE 5th Eurasia Conference on IOT, Communication and Engineering (ECICE), 27 Oct. 2023, Refereed
Corresponding

Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition
Toshinori Sato; Hiroyuki Hama; Tomoaki Ukezono
2023 20th International SoC Design Conference (ISOCC), 25 Oct. 2023, Refereed
Lead

Leveraging Approximate Computing for IoT Image Transmission
Hiroyuki Hama; Tomoaki Ukezono; Toshinori Sato
2023 20th International SoC Design Conference (ISOCC), 25 Oct. 2023, Refereed
Corresponding

Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders
Hiroyuki Hama; Toshinori Sato
2023 IEEE 12th Global Conference on Consumer Electronics (GCCE), 10 Oct. 2023, Refereed
Corresponding

Evaluating Sign Error Correction for Approximate Adders Employing ECG Signal Processing
Hiroyuki Hama; Toshinori Sato
2023 10th International Conference on Electrical Engineering, Computer Science and Informatics (EECSI), 20 Sep. 2023, Refereed
Corresponding

Negative Impact of Approximated Signed Addition on Power Reduction
Hiroyuki Hama; Tomoaki Ukezono; Toshinori Sato
2023 International Symposium on Devices, Circuits and Systems, May 2023, :1 - 6, Refereed
Corresponding

An Accuracy-Controllable Approximate Adder for FPGAs
Masaki Sano; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama; Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
4th International Symposium on Advanced Technologies and Applications in the Internet of Things, Aug. 2022, :60 - 66, Refereed

Reducing Power Consumption Using Approximate Encoding for CNN Accelerators at the Edge
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
32nd ACM Great Lakes Symposium on VLSI, 07 Jun. 2022, Refereed
Last

Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations
Sato Toshinori; Tomoaki UKEZONO
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Sep. 2020, E103-A(9):1028 - 1036, Refereed
Lead

A Dynamically Configurable Approximate Array Multiplier with Exact Mode
Sato Toshinori; Tomoaki UKEZONO
5th International Conference on Computer and Communication Systems, 18 May 2020, Refereed
Lead

An Accuracy-Configurable Adder for Low-Power Applications
Yang Tongxin; Sato Toshinori; Tomoaki UKEZONO
IEICE Transactions on Electronics, Mar. 2020, E103-C(3):68 - 76, Refereed

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance
Sato Toshinori; Tomoaki Ukezono
24th IEEE Pacific Rim International Symposium on Dependable Computing, Dec. 2019, Refereed
Lead

Correcting Sign Calculation Errors in Configurable Approximations
Sato Toshinori; Tomoaki Ukezono
15th IEEE Asia Pacific Conference on Circuits and Systems, Nov. 2019, Refereed
Lead

Tolerating Aging-Induced Timing Violations via Configurable Approximations
Sato Toshinori; Tomoaki Ukezono
8th IEEE Global Conference on Consumer Electronics, 18 Oct. 2019, Refereed
Lead

On Applications of Configurable Approximation to Irregular Voltage
Sato Toshinori; Tomoaki Ukezono
5th IEEE Nordic Circuits and Systems Conference, Oct. 2019, Refereed
Lead

An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area
Tongxin Yang; Toshinori Sato; Tomoaki Ukezono
IEEE Computer Society Annual Symposium on VLSI, Jul. 2019, Refereed
Corresponding

Design of a Low-Power and Small-Area Approximate Multiplier Using First the Approximate and Then the Accurate Compression Method
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
29th ACM Great Lakes Symposium on VLSI, May 2019, Refereed
Last

Trading Accuracy for Power with a Configurable Approximate Adder
Toshinori Sato; Tongxin Yang; Tomoaki Ukezono
IEICE Transactions on Electronics, Apr. 2019, E102-C(4):260 - 268, Refereed
Lead

A Low-Power Approximate Multiply-Add Unit
Tongxin Yang; Toshinori Sato; Tomoaki Ukezono
2nd International Symposium on Devices, Circuits and Systems, Mar. 2019, Refereed
Corresponding

Design and Analysis of Approximate Multipliers with a Tree Compressor
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Mar. 2019, E102-A(3):532 - 543, Refereed
Last

Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2018, E101-A(12), Refereed
Last

Approximate Adder Genaration for Image Processing Using Convolutional Neural Network
Ryuta Ishida; Toshinori Sato; Tomoaki Ukezono
15th International SoC Design Conference, Nov. 2018, Refereed
Corresponding

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder
Sato Toshinori; Tomoaki Ukezono
15th International SoC Design Conference, Nov. 2018, Refereed
Lead

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing
Hiroyuki Baba; Tongxin Yang; Masahiro Inoue; Kaori Tajima; Tomoaki Ukezono; Toshinori Sato
IEEE Computer Society Annual Symposium on VLSI, Jul. 2018, Refereed
Corresponding

A low-power configurable adder for approximate applications
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
Proceedings - International Symposium on Quality Electronic Design, ISQED, 09 May 2018, 2018-:347 - 352, Refereed
Last

A Low-Power Yet High-Speed Configurable Adder for Approximate Computing
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
51st International Symposium on Circuits and Systems, May 2018, Refereed
Last

A low-power high-speed accuracy-controllable approximate multiplier design
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 20 Feb. 2018, 2018-:605 - 610, Refereed

Low-power and high-speed approximate multiplier design with a tree compressor
Tongxin Yang; Tomoaki Ukezono; Toshinori Sato
Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, 22 Nov. 2017, :89 - 96, Refereed

Optimizing power heterogeneous functional units for dynamic and static power reduction
Toshinori Sato; Yoshimi Shibata
Electronics, 10 Dec. 2014, 3(4):661 - 674, Refereed
Lead

カナリアFF
佐藤寿倫; 矢野憲; 安浦寛人
日本信頼性学会誌「信頼性」, Dec. 2013, 35(8):452
Lead

画像認識型ライントレーサのHW/SW同時開発を題材とするPBLの実践・評価
橋本, 浩二; 馬場, 明也; モシニャガ, ワシリー; 森元, 逞; 佐藤, 寿倫
組込みシステムシンポジウム2013論文集, 09 Oct. 2013, 2013:173 - 174, Refereed

Improving Timing Error Tolerance without Impact on Chip Area and Power Consumption
Ken Yano; Takanori Hayashida; Toshinori Sato
15th International Symposium on Quality Electronic Design, Mar. 2013, Refereed

Analysis of SER Improvement by Radiation Hardened Latches
Sato Toshinori; HAYASHIDA Takanori; YANO Ken
18th IEEE Pacific Rim International Symposium on Dependable Computing, 18 Nov. 2012, Refereed
Lead

Guidelines for Mitigating NBTI Degradation in On-chip Memories
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida
12th International Symposium on Communications and Information Technologies, 02 Oct. 2012, Refereed
Corresponding

Simultaneous Dynamic and Static Power Reduction Utilizing Power Heterogeneous Functional Units
Yoshimi Shibata; Takanori Hayashida; Toshinori Sato; Shinya Takahashi
27th International Technical Conference on Circuits/Systems, Computers and Communications, 17 Jul. 2012, Refereed
Corresponding

Dynamically Reducing Overestimated Design Margin of MultiCores
Toshinori Sato; Takanori Hayashida; Ken Yano
10th International Conference on High Performance Computing & Simulation, 04 Jul. 2012, Refereed
Lead

Importance of Single-Core Performance in the Multicore Era
Toshinori Sato; Hideki Mori; Rikiya Yano; Takanori Hayashida
35th Australasian Computer Science Conference, Jan. 2012, Refereed
Lead

Possibilities to Miss Predicting Timing Errors in Canary Flip-flops
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida
54th IEEE International Midwest Symposium on Circuits and Systems, Aug. 2011, Refereed
Corresponding

Multicore Power Management Utilizing Error-Predicting Flip-flop
Toshinori Sato; Takahito Yoshiki; Takanori Hayashida
4th International Workshop on Multi-Core Computing Systems, 01 Jul. 2011, Refereed
Lead

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2011, E94C(4):520 - 529, Refereed

A Selective Replacement Method for Timing-Error-Predicting Flip-Flops
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida
2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011, 21(6), Refereed
Corresponding

A Replacement Strategy for Canary Flip-Flops
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
16th IEEE Pacific Rim International Symposium on Dependable Computing, 15 Dec. 2010, :227 - 228, Refereed
Corresponding

MultiCore Energy Reduction Utilizing Canary FF
Yoshimi Otsuka; Toshinori Sato; Takahito Yoshiki; Takanori Hayashida
10th International Symposium on Communications and Information Technologies, 29 Oct. 2010, Refereed
Corresponding

A Case Study of Short Term Cell-Flipping Technique for Mitigating NBTI Degradation on Cache
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
2nd Asia Symposium on Quality Electronic Design, 04 Aug. 2010, Refereed

Signal Probability Control for Relieving NBTI in SRAM Cells
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
11th International Symposium on Quality Electronic Design, 24 Mar. 2010, :198 - 205, Refereed

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
Yuji Kunitake; Kazuhiro Mima; Toshinori Sato; Hiroto Yasuura
IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2009, E92C(4):483 - 491, Refereed

A Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement
Shingo Watanabe; Masanori Hashimoto; Toshinori Sato
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, :401 - +, Refereed

Uncriticality-directed Scheduling for Tackling Variation and Power Challenges
Toshinori Sato; Shingo Watanabe
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, :820 - +, Refereed
Lead

Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops
Yuji Kunitgake; Toshinori Sato; Hiroto Yasuura
16th IFIP/IEEE International Conference on Very Large Scale Integration, 15 Oct. 2008, Refereed

A simple mechanism for collapsing instructions under timing speculation
Toshinori Sato
IEICE TRANSACTIONS ON ELECTRONICS, Sep. 2008, E91C(9):1394 - 1401, Refereed

タイミング歩留まり改善を目的とする演算カスケーディング
Shingo Watanabe; Masanori Hashimoto; Toshinori Sato
IPSJ Transactions on Advanced Computing Systems, Aug. 2008, 1(2):12 - 21, Refereed

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
Tohru Ishihara; Seiichiro Yamaguchi; Yuriko Ishitobi; Tadayuki Matsumura; Yuji Kunitake; Yuichiro Oyama; Yusuke Kaneda; Masanori Muroyama; Toshinori Sato
6th IEEE Symposium on Application Specific Processors, 08 Jun. 2008, :83 - 88, Refereed

ばらつき耐性を持つカナリアFFを利用したデザインマージン削減による省電力化
佐藤寿倫; 国武勇次
情報処理学会論文誌, Jun. 2008, 49(6):2029 - 2042, Refereed

マルチコアプロセッサのための電力・性能間トレードオフを考慮したディペンダビリティ選択法
佐藤寿倫; 舟木敏正
情報処理学会論文誌, Jun. 2008, 49(6):2005 - 2015, Refereed

Uncriticality-directed Low-power Instruction Scheduling
Shingo Watanabe; Toshinori Sato
IEEE Computer Society Annual Symposium on VLSI, 07 Apr. 2008, Refereed

A low-power instruction issue queue for microprocessors
Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato
IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2008, E91C(4):400 - 409, Refereed

Instruction Scheduling for Variation-originated Variable Latencies
Toshinori Sato; Shingo Watanabe
9th International Symposium on Quality Electronic Design, 17 Mar. 2008, Refereed

Dependability, power, and performance trade-off on a multicore processor
Toshinori Sato; Toshimasa Funaki
2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, :684 - +, Refereed

Formulating MITF for a Multicore Processor with SEU Tolerance
Toshimasa Funaki; Toshinori Sato
11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, :234 - +, Refereed

Folding active list for high performance and low power
Yuichiro Imaizumi; Toshinori Sato
HIGH-PERFORMANCE COMPUTING, 2008, 4759:33 - +, Refereed

Architecture Challenge on SoC Design with Unreliable Transistors
Toshinori Sato
International SoC Design Conference, Oct. 2007, Refereed

Exploiting Input Variations for Energy Reduction
Toshinori Sato; Yuji Kunitake
17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep. 2007, Refereed

Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism
Toshinori Sato; Yuu Tanaka; Hidenori Sato; Toshimasa Funaki; Takenori Koshiro; Akihiro Chiyonobu
International Journal of Computers and their Applications, Jun. 2007, 14(2):79 - 91, Refereed

データの重要度を利用したキャッシュメモリの省電力化
Akihiro Chiyonobu; Seiichiro Fujii; Toshinori Sato
IPSJ Transactions on Advanced Computing Systems, May 2007, 48(SIG8(ACS18)):114 - 126, Refereed

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
Toshinori Sato; Yuji Kunitake
8th International Symposium on Quality Electronic Design, Mar. 2007, :539 - 544, Refereed

Challenges in Evaluations for a Typical-Case Design Methodology
Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato
8th International Symposium on Quality Electronic Design, Mar. 2007, :374 - 379, Refereed

Indirect tag search mechanism for instruction window energy reduction
Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato
2007 CIT: 7TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY, PROCEEDINGS, 2007, :841 - +, Refereed

Power-performance trade-off of a dependable multicore processor
Toshinori Sato; Toshimasa Funaki
13TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2007, :268 - +, Refereed

キャッシュミス情報を利用する省電力命令スケジューリング
Akihiro Chiyonobu; Toshinori Sato
IEICE Transactions, Dec. 2006, J89-D(12):2590 - 2601, Refereed

タイミング違反を許容する省電力加算器における違反検出回路の高速化
Mikio Yamahara; Kazuhiro Mima; Akihiro Chiyonobu; Toshinori Sato
IPSJ Transactions on Advanced Computing Systems, Nov. 2006, 47(SIG18(ACS16)):65 - 79, Refereed

A Leakage-Energy-Reduction Technique for Cache Memories in Embedded Processors
Seiichiro Fujii; Akihito Sakanaka; Akihiro Chiyonobu; Toshinori Sato
Journal of Embedded Computing, Oct. 2006, 2(1):49 - 55, Refereed

Energy-Efficient Instruction Scheduling Utilizing Cache Miss Information
Akihiro Chiyonobu; Toshinori Sato
ACM SIGARCH Computer Architecture News, Mar. 2006, 34(1):65 - 70

Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors
Toshinori Sato; Akihiro Chiyonobu; Kazuki Joe
9th International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, Jan. 2006, Refereed

Evaluating the impact of fault recovery on superscalar processor performance
Toshinori Sato; Akihiro Chiyonobu
12TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS, 2006, :369 - +, Refereed

Improving energy efficiency via speculative multithreading on MultiCore processors
Toshinori Sato; Yuu Tanaka; Hidenori Sato; Toshimasa Funaki; Takenori Koushiro; Akihiro Chiyonobu
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2006, 4148:553 - 562, Refereed

省電力とプロセッサ
佐藤寿倫
情報処理学会学会誌, Nov. 2005, 46(11):1212 - 1217

Energy-Efficient Instruction Scheduling Exploiting Memory Access Slack
Akihiro Chiyonobu; Toshinori Sato
Workshop on Memory Performance: Dealing with Applications, Systems, and Architecture, Sep. 2005, Refereed

An energy-efficient clustered superscalar processor
T Sato; A Chiyonobu
IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2005, E88C(4):544 - 551, Refereed

Exploiting Trivial Computation in Dependable Processors
Toshinori Sato
20th International Conference on Computers and Their Applications, Mar. 2005, Refereed

Profiling with Helper Threads
Takamasa Tokunaga; Toshinori Sato
International Conference on Parallel and Distributed Computing and Networks, Feb. 2005, Refereed

Exploiting Sub-word Parallelism for Dependable Processors
Toshinori Sato
5th International Conference on Automation & Information, Nov. 2004, 6(1):1051 - 1056, Refereed

Hardware Cost Reduction in Fault Detection Mechanism for Constructive Timing Violation Technique
Kazuhiro Mima; Toshinori Sato
10th International Symposium on Integrated Circuits, Devices and Systems, Sep. 2004, Refereed

A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion
Akio Kodama; Toshinori Sato
10th International Symposium on Integrated Circuits, Devices and Systems, Sep. 2004, Refereed

Non-Uniform Set Associative Caches for Power-Aware Embedded Processors
Seiichiro Fujii; Toshinori Sato
International Conference on Embedded and Ubiquitous Computing, Aug. 2004, Refereed

Exploring Configuration of Dual Speed Pipelines for Criticality-based Energy-efficient Processors
Akihiro Chiyonobu; Toshinori Sato
8th World Multiconference on Systemics, Cybernetics and Informatics, Jul. 2004, Refereed

The Potential in Energy Efficiency of a Speculative Chip-Multiprocessor
Yuu Tanaka; Toshinori Sato; Takenori Koushiro
16th Symposium on Parallelism in Algorithms and Architectures, Jun. 2004, Refereed

Investigating Heterogeneous Combination of Functional Units for a Criticality-based Low-power Processor Architecture
Akihiro Chiyonobu; Toshinori Sato
3rd International Symposium on Information and Communication Technologies, Jun. 2004, Refereed

FPGA/DSPベースシステムによる組込みシステム設計教育
田中康一郎; 林悠平; 澤田直; 佐藤寿倫; 有田五次郎
電子情報通信学会論文誌 D1, Jun. 2004, J87-D1(6):640 - 640, Refereed

A Static and Dynamic Energy Reduction Technique for I-Cache and BTB in Embedded Processors
Hidenori Sato; Toshinori Sato
Asia and South Pacific Design Automation Conference, Jan. 2004, Refereed

低消費電力指向マルチスレッドプロセッサのための低コスト値予測機構の検討
神代剛典; 佐藤寿倫
情報処理学会論文誌コンピューティングシステム, Jan. 2004, 45(SIG 1(ACS 4)):43 - 53, Refereed

A Field-Customizable and Runtime-Adaptable Microarchitecture
Toshinori Sato; Daisuke Morishita
2nd International Conference on Field-Programmable Technology, Dec. 2003, :328 - 331, Refereed

A transparent transient faults tolerance mechanism for superscalar processors
T Sato
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Dec. 2003, E86D(12):2508 - 2516, Refereed

Combining variable latency pipeline with instruction reuse for execution latency reduction
Toshinori Sato; Itsujiro Arita
Systems and Computers in Japan, 15 Nov. 2003, 34(12):11 - 21

Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation
Asami Tanino; Toshinori Sato
16th International Conference on Computer Applications in Industry and Engineering, Nov. 2003, Refereed

Exploiting Instruction Redundancy for Transient Fault Tolerance
Toshinori Sato
18th International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2003, Refereed

Reducing Static Energy of Cache Memories via Prediction-Table-less Way Prediction
Akihito Sakanaka; Toshinori Sato
13th International Workshop on Power And Timing Modeling, Sep. 2003, Refereed

低消費電力プロセッサアーキテクチャ向けクリティカルパス予測器の評価
千代延昭宏; 佐藤寿倫; 有田五次郎
電子情報通信学会論文誌 C, Aug. 2003, J86-C(8):826 - 835, Refereed

Design of Hardware/Software Co-Design Emvironment Using SpecC-based Tools
Yuhei Hayashi; Koichiro Tanaka; Toshinori Sato; Itsujiro Arita
International Technical Conference on Circuits/Systems, Computers and Communications, Jul. 2003, Refereed

A Trace-Level Value Predictor for Contrail Processors
Takenori Koushiro; Toshinori Sato; Itujiro Arita
ACM SIGARCH Computer Architecture News, Jun. 2003, 31(3):42 - 47

Correlation-based critical path predictors for low power microprocessors
Akihiro Chiyonobu; Toshinori Sato; Itsujiro Arita
Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003, 2003-:11 - 18, Refereed

Constructive timing violation for improving energy efficiency
T Sato; Arita, I
COMPILERS AND OPERATING SYSTEMS FOR LOW POWER, 2003, :137 - 153, Refereed

A leakage-energy-reduction technique for highly-associative caches in embedded systems
Akihito Sakanaka; Seiichirou Fujii; Toshinori Sato
Proceedings of the 2003 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '03, 2003, 32(3):50 - 54, Refereed

可変レイテンシパイプライン技術と演算結果再利用技術の併用による演算レイテンシ削減
佐藤寿倫; 有田五次郎
電子情報通信学会論文誌 D-I, Dec. 2002, J85-D-I(12):1103 - 1113, Refereed

Evaluating influence of compiler optimizations on data speculation
T Sato; K Sugitani; A Hamano; Arita, I
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, Nov. 2002, 18(6):1027 - 1036, Refereed

Reducing Energy Consumption via Low-Cost Value Prediction
Toshinori Sato; Itsujiro Arita
12th International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2002, Refereed

Simplifying Instruction Issue Logic in Superscalar Processors
Toshinori Sato; Itsujiro Arita
EUROMICRO Symposium on Digital System Design: Architectures, Methods and Tools, Sep. 2002, Refereed

Design and Implementation of FPGA/DSP Based PCI Card
Koichiro Tanaka; Yuichi Iwaya; Yuhei Hayashi; Toshinori Sato; Itsujiro Arita
Workshop on Logic and Synthesis for Programmable Devices, Aug. 2002, Refereed

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization
Toshiyuki Yamamoto; Kou Morita; Toshinori Sato; Itsujiro Arita
International Conference on Parallel and Distributed Processing Techniques and Applications, Jun. 2002, Refereed

Potential of constructive timing-violation
T Sato; Arita, I
IEICE TRANSACTIONS ON ELECTRONICS, Feb. 2002, E85C(2):323 - 330, Refereed

Power and Performance Fitting in Nanometer Design
Toshinori Sato; Takenori Koushiro; Akihiro Chiyonobu; Itujiro Arita
5th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Jan. 2002, Refereed

Low-cost value predictors using frequent value locality
Toshinori Sato; Itsujiro Arita
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2002, 2327:106 - 119, Refereed

Evaluating the impact of reissued instructions on data speculative processor performance
T Sato
MICROPROCESSORS AND MICROSYSTEMS, Jan. 2002, 25(9-10):469 - 482, Refereed

The KIT COSMOS Processor: A Low-Complexity Superscalar Processor
Toshinori Sato; Toshiyuki Yamamoto; Itsujiro Arita
International Journal of Computer & Information Science, Dec. 2001, 2(4):182 - 190, Refereed

In Search of Efficient Reliable Processor Design
Toshinori Sato; Itsujiro Arita
30th International Conference on Parallel Processing, Sep. 2001, Refereed

Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Toshinori Sato; Itsujiro Arita
7th International Euro-Par Conference, Aug. 2001, Refereed

The KIT COSMOS Processor: Some Ideas on Realizing Complexity-Effective Superscalar Processors
Toshinori Sato; Toshiyuki Yamamoto; Itsujiro Arita
2nd International Conference on Software Engineering, Artificial Intelligence, Networking & Parallel/Distributed Computing, Aug. 2001, Refereed

Tolerating Transient Faults through an Instruction Reissue Mechanism
Toshinori Sato; Itsujiro Arita
14th International Conference on Parallel and Distributed Computing Systems, Aug. 2001, Refereed

Influence of Compiler Optimizations on Value Prediction
Toshinori Sato; Akihiko Hamano; Kiichi Sugitani; Itsujiro Arita
9th International Conference on High Performance Computing and Networking Europe, Jun. 2001, Refereed

Evaluating low-cost fault-tolerance mechanism for microprocessors on multimedia applications
Toshinori Sato; Itsujiro Arita
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC, 2001, 2001-:225 - 232, Refereed

Evaluating Effect of Optimization Level on Value Predictability
Kiichi Sugitani; Akihiko Hamano; Toshinori Sato; Itsujiro Arita
4th International Conference on Algorithms and Architectures for Parallel Processing, Dec. 2000, Refereed

Comprehensive Evaluation of an Instruction Reissue Mechanism
Toshinori Sato; Itsujiro Arita
5th International Symposium on Parallel Architectures, Algorithms and Networks, Dec. 2000, Refereed

Evaluating trace cache on moderate-scale processors
T Sato
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, Nov. 2000, 147(6):369 - 374, Refereed

Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism
T Sato
JOURNAL OF SYSTEMS ARCHITECTURE, Nov. 2000, 46(13):1231 - 1252, Refereed

Partial Resolution in Data Value Predictors
Toshinori Sato; Itsujiro Arita
29th International Conference on Parallel Processing, Aug. 2000, Refereed

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3-D graphics computing
N Ide; M Hirano; Y Endo; S Yoshioka; H Murakami; A Kunimatsu; T Sato; T Kamei; T Okada; M Suzuoki
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Jul. 2000, 35(7):1025 - 1033, Refereed

The KIT COSMOS Processor: Introducing CONDOR
Toshinori Sato; Itsujiro Arita
International Conference on Parallel and Distributed Processing Techniques and Applications, Jun. 2000, Refereed

Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values
Toshinori Sato; Itsujiro Arita
14th International Conference on Supercomputing, May 2000, :196 - 205, Refereed

Vector unit architecture for emotion synthesis
A Kunimatsu; N Ide; T Sato; Y Endo; H Murakami; T Kamei; M Hirano; F Ishihara; H Tago; M Oka; A Ohba; T Yutaka; T Okada; M Suzuoki
IEEE MICRO, Mar. 2000, 20(2):40 - 47, Refereed

300MHz Design Methodology of VU for Emotion Synthesis
Takayuki Kamei; Hideki Takeda; Yukio Ootagro; Takayoshi Shimazawa; Kazuhiko Tachibana; Shinichi Kawakami; Seiji Norimatsu; Fujio Ishihara; Toshinori Sato; Hiroaki Murakami; Nobuhiro Ide; Yukio Endo; Atsushi Kunimatu
Asia and South Pacific Design Automation Conference, Jan. 2000, Refereed

A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism
Toshinori Sato
EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools, Sep. 1999, Refereed

A simulation study of combining load value and address predictors
T Sato
INTERNATIONAL JOURNAL OF HIGH SPEED COMPUTING, Sep. 1999, 10(3):301 - 325, Refereed

Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure
Toshinori Sato
5th International Euro-Par Conference, Aug. 1999, Refereed

Profile-based Selection of Load Value and Address Predictors
Toshinori Sato
International Symposium on High Performance Computing, May 1999, Refereed

命令再発行機構によるデータアドレス予測に基づく投機実行の効果改善
佐藤寿倫
情報処理学会論文誌, May 1999, 40(5):2093 - 2108, Refereed

2ホップアドレス名前替えを用いたロード命令の投機的実行
佐藤寿倫
2109-2118, May 1999, 40(5):2109 - 2118, Refereed

Reducing Miss Penalty of Load Value Prediction using Load Address Prediction
Toshinori Sato
4th Australasian Computer Architecture Conference, Jan. 1999, Refereed

First Step to Combining Control and Data Speculation
Toshinori Sato
2nd International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Oct. 1998, Refereed

Load Value Prediction using Two-Hop Reference Address Renaming
Toshinori Sato
4th International Conference on Computer Science and Informatics, Oct. 1998, Refereed

A microprocessor architecture utilizing histories of dynamic sequences saved in distributed memories
T Sato
IEICE TRANSACTIONS ON ELECTRONICS, Sep. 1998, E81C(9):1398 - 1407, Refereed

Data Dependence Speculation using Data Address Prediction and its Enhancement with Instruction Reissue
Toshinori Sato
EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools, Aug. 1998, Refereed

Resolving load data dependency using tunneling-load technique
T Sato
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Aug. 1998, E81D(8):829 - 838, Refereed

2レベル適応型分岐予測機構のパターン履歴表におけるタグの影響
佐藤寿倫
電子情報通信学会論文誌 D-I,, Jun. 1998, J81-D-I(6):728 - 737, Refereed

Data Dependence Path Reduction with Tunneling Load Instructions
Toshinori Sato
International Symposium on High Performance Computing, Nov. 1997, :119 - 130, Refereed

Speculative Resolution of Ambiguous Memory Aliasing
Toshinori Sato
1st International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Oct. 1997, Refereed

Hiding data cache latency with load address prediction
T Sato; H Fujii; S Suzuki
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Nov. 1996, E79D(11):1523 - 1532, Refereed

高性能低消費電力プロセッサR3900
永松正人; 佐藤寿倫; 田胡治之
東芝レビュー, Dec. 1995, 50(12):883 - 886

Evaluation of Architecture-level Power Estimation for CMOS RISC Processors
Toshinori Sato; Yukio Ootaguro; Masato Nagamatsu; Haruyuki Tago
Symposium on Low Power Electronics, Oct. 1995, :44 - 45, Refereed

Power and Performance Simulator:ESP and its Application for 100MIPS/W Class RISC Design
Toshinori Sato; Masato Nagamatsu; Haruyuki Tago
Symposium on Low Power Electronics, Oct. 1994, :46 - 47, Refereed

PERFORMANCE EVALUATION OF A PROCESSING ELEMENT FOR AN ON-CHIP MULTIPROCESSOR
M TAKAHASHI; H FUJII; E KANEKO; T YOSHIDA; T SATO; H TAKANO; H TAGO; S SUZUKI; N GOTO
IEICE TRANSACTIONS ON ELECTRONICS, Jul. 1994, E77C(7):1092 - 1100, Refereed

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors
N. Ide; H. Fukuhisa; Y. Kondo; T. Yoshida; M. Nagamatu; J. Mori; I. Yamazaki; K. Ueno
Proceedings of the Custom Integrated Circuits Conference, 1992, 32:30.2.4 - 109, Refereed

対称性保持の制約を扱えるレイアウトコンパクションアルゴリズム
奥田亮輔; 佐藤寿倫; 小野寺秀俊; 田丸啓吉
電子情報通信学会論文誌 A, Mar. 1990, J73-A(3):536 - 543, Refereed

An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints
Ryousuke Okuda; Toshinori Sato; Hidetoshi Onodera; Keikichi Tamaru
International Conference on Computer-Aided Design, Nov. 1989, Refereed

A Low-Power Small-Area MAC Unit for Accuracy-Scalable Approximate Computing
Sato Toshinori; Tomoaki UKEZONO
Fukuoka University Review of Technological Sciences, Mar. 2020, 103・104:1 - 8

CMAを用いた画像先鋭化処理専用回路の低消費電力化改善
佐藤 寿倫; 請園 智玲
福岡大学工学集報, Mar. 2019, (101・102):43 - 49

近似乗算器の内部構成に関する検討 (VLSI設計技術) -- (デザインガイア2017 : VLSI設計の新しい大地)
井上 晶仁; 田島 加織; 馬場 裕之; ヨウ ドウキン; 請園 智玲; 佐藤 寿倫
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 06 Nov. 2017, 117(273):13 - 18

Typical Case Oriented Design Approach by Timing Error Prediction to Tolerate Process Variability
Ken Yano; Toshinori Sato
Fukuoka University Review of Technological Sciences, Sep. 2015, 95(95):7 - 16

携帯情報端末向け高性能プロセッサの消費電力削減
佐藤 寿倫; 高橋 伸弥
福岡大学研究部論集 F：推奨研究編, Mar. 2015, 2:19 - 24

安心・安全な社会基盤のためのLSI
福岡大学研究推進部 Research, Sep. 2008, 13(3):3 - 4

キャッシュ非共有型マルチコアプロセッサにおけるキャッシュの性能改善に関する研究
ITO Yoshitaka; CHIYONOBU Akihiro; SATO Toshinori
IEICE technical report, 08 Dec. 2006, 106(436):63 - 68

新しいクリティカルパス判定基準を用いたクリティカルパス予測器の評価
CHIYONOBU AKIHIRO; SATO TOSHINORI
IPSJ SIG Notes, 31 Jul. 2006, 2006(88):61 - 66

温度を考慮するアーキテクチャの検討のための物理レジスタアクセス頻度の特徴調査
SATO Toshinori; KUNITAKE Yuji; CHIYONOBU Akihiro
IPSJ SIG Notes, 08 Jun. 2006, 2006(62):37 - 42

タイミング違反を利用するマイクロアーキテクチャの演算器における遅延を考慮した評価
KUNITAKE Yuji; CHIYONOBU Akihiro; TANAKA Koichiro; SATO Toshinori
IPSJ SIG Notes, 08 Jun. 2006, 2006(62):43 - 48

温度を考慮するアーキテクチャの検討のための物理レジスタアクセス頻度の特徴調査
SATO Toshinori; KUNITAKE Yuji; CHIYONOBU Akihiro
IEICE technical report, 01 Jun. 2006, 106(92):37 - 42

タイミング違反を利用するマイクロアーキテクチャの演算器における遅延を考慮した評価
KUNITAKE Yuji; CHIYONOBU Akihiro; TANAKA Koichiro; SATO Toshinori
IEICE technical report, 01 Jun. 2006, 106(92):43 - 48

タイミング違反を利用した省電力プロセッサにおける履歴を用いた性能低下抑制手法
CHIYONOBU Akihiro; MIMA Kazuhiro; SATO Toshinori
IPSJ SIG Notes, 27 Feb. 2006, 2006(20):145 - 150

命令カスケーディングにおける典型的パス遅延の効用
SATO Toshinori; CHIYONOBU Akihiro
IEICE technical report, 16 Dec. 2005, 105(487):19 - 24

命令の振る舞いを利用した消費電力削減に関する検討
CHIYONOBU Akihiro; SATO Toshinori
IPSJ SIG Notes, 31 Jul. 2004, 2004(80):169 - 174

値予測を用いた命令流分割によるエネルギー消費量削減
KOSHIRO TAKENORI; SATO TOSHINORI; ARITA ITSUJIRO
IPSJ SIG Notes, 27 Nov. 2002, 2002(112):95 - 100

センサフュージョン技術の開発と応用事例
佐藤 寿倫; 請園 智玲, Joint work
技術情報協会, Jan. 2019

VLSI Design and Test for Systems Dependability
Shojiro Asai
Springer, 21 Jul. 2018
9784431565925

コンピュータアーキテクチャ 定量的アプローチ 第5版
中條拓伯; 天野英晴; 鈴木貢; 吉瀬謙二; 佐藤寿倫, Joint translation
翔泳社, Mar. 2014
9784798126234

知識ベース, 6群5編 コンピュータアーキテクチャ(II)先進的
馬場敬信; 天野英晴; 合田憲人; 佐藤寿倫, Joint editor
電子情報通信学会, May 2010

知識ベース, 6群5編1章 命令レベル並列コンピュータ
佐藤寿倫; 安藤秀樹; 吉瀬謙二, Joint work
電子情報通信学会, May 2010

知識ベース, 6群5編4章 ベクトルコンピュータ
佐藤寿倫; 平澤将一; 林宏雄, Joint work
電子情報通信学会, May 2010

知識ベース, 6群5編2章 スレッドレベル並列コンピュータ
佐藤寿倫; 小林良太郎; 中條拓伯; 大津金光, Joint work
電子情報通信学会, May 2010

コンピュータアーキテクチャ 定量的アプローチ 第4版
中條 拓伯; 天野 英晴; 吉瀬 謙二; 佐藤 寿倫, Joint translation
翔泳社, Feb. 2008

High-Performance Computing
Jesus Labarta; Kazuki Joe; Toshinori Sato, Joint editor
Springer-Verlag, Jan. 2008

C-Packアルゴリズムを拡張した主記憶データの非可逆圧縮手法
馬場裕之; 請園智玲; 佐藤寿倫
情報処理学会 第81回全国大会, Mar. 2019, 情報処理学会

カラー画像を対象とした近似加算器を用いた画像先鋭化ハードウェアの評価
請園智玲; 福田結菜; 佐藤寿倫
情報処理学会 第81回全国大会, Mar. 2019, 情報処理学会

手書き数字認識ニューラルネットワークにおける近似乗算器の評価
佐藤寿倫; 請園智玲
情報処理学会 第81回全国大会, Mar. 2019, 情報処理学会

Redis向けYCSBベンチマーク実行時のFPCによる消費電力削減
馬場裕之; 寺﨑雅紀; 請園智玲; 佐藤寿倫
第17回情報科学技術フォーラム, Sep. 2018

A Carry-Predicting Full Adder for Accuracy-Scalable Computing
Hiroyuki Baba; Tongxin Yang; Masahiro Inoue; Kaori Tajima; Tomoaki Ukezono; Toshinori Sato
21st Workshop on Synthesis And System Integration of Mixed Information technologies, Mar. 2018

CMAを用いた画像先鋭化処理専用回路の低消費電力化
田島加織; 井上晶仁; 馬場裕之; Tongxin Yang; 請園智玲; 佐藤寿倫
電子情報通信学会技術研究報告 VLD, 18 Jan. 2018

KVSデータベースRedisからのデータアクセス局所性の解析
馬場裕之; 請園智玲; 佐藤寿倫
電子情報通信学会技術研究報告 CPSY, Nov. 2017

近似乗算器の内部構成に関する検討
井上晶仁; 田島加織; 馬場裕之; Tongxin Yang; 請園智玲; 佐藤寿倫
電子情報通信学会技術研究報告 VLD, Nov. 2017

動的な桁上げマスクを可能にする近似加算器の特性評価
Tongxin Yang; 請園智玲; 佐藤寿倫
電子情報通信学会 基礎・境界ソサイエティ/NOLTAソサイエティ大会, Sep. 2017

ガウシアンカーネルの近似値化によるハードウェア単純化の検討
井上晶仁; 田島加織; Tongxin Yang; 請園智玲; 佐藤寿倫
第70回 電気・情報関係学会九州支部連合大会, Sep. 2017

Flashメモリ上のKey-Value Storeのデータ構造のためのIoT向け低消費電力マイクロアーキテクチャの評価
馬場裕之; 請園智玲; 佐藤寿倫
情報処理学会 第79回全国大会, Mar. 2017

下位レベルキャッシュメモリへのアクセスフィルタによるタグ参照電力の削減
石田隆太; 請園智玲; 佐藤寿倫
情報処理学会 第79回全国大会, Mar. 2017

Flashメモリ上のKey-Value Storeのデータ構造のためのIoT向け低消費電力マイクロアーキテクチャの検討
Tomoaki UKEZONO; Sato Toshinori
第18回 IEEE広島支部 学生シンポジウム, 19 Nov. 2016, IEEE

次世代不揮発性メモリを用いた省電力キャッシュに関する研究
岡本駿; 佐藤寿倫
2015年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2015

GPGPUプロクラムにおけるプログラミング容易化の検討,
箱田雄太; 佐藤寿倫
2015年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2015

動作時のコア数と周波数がプログラムあたりの消費電力に与える影響の考察
林田哲; 佐藤寿倫
2015年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2015

不揮発性メモリを用いる省電力キャッシュに関する研究
吉永亮太
第67回電気・情報関係学会九州支部連合大会, 19 Sep. 2014

2命令インオーダ発行仕様のスーパースカラプロセッサの設計
枝元正寛; 林田隆則; 佐藤寿倫
情報処理学会研究報告 ARC, Jan. 2014

画像認識型ライントレーサのHW/SW同時開発を題材とするPBLの実践・評価
Sato Toshinori; HASHIMOTO Koji; MORIMOTO Tsuyoshi
組込みシステムシンポジウム2013, Oct. 2013

高性能・省電力プロセッサ向けメモリスケジューリング手法の調査
吉田康洋; 林田隆則; 佐藤寿倫
電子情報通信学会九州支部学生講演会, Sep. 2013

巡回セールスマン問題を題材としたOpenCLによる並列化
Sato Toshinori; HAYASHIDA Takanori
情報処理学会九州支部 火の国情報シンポジウム, Mar. 2013

Analysis of Better-Than-Worst-Case System Design Methodology by Using Canary Flip-Flops
Ken Yano; Mitsugu Ogawa; Ryota Yoshinaga; Takahito Yoshiki; Takanori Hayashida; Toshinori Sato
Design, Automation & Test in Europe Conference & Exhibition, Mar. 2013

Analysis of SER Improvement by Soft Error Tolerant Latches
Ken Yano; Takanori Hayashida; Toshinori Sato
SWoPP 2012, 02 Aug. 2012

モンテカルロシミュレーションによる ソフトエラー耐性ラッチ、SRAMの信頼性評価
YANO Ken; HAYASHIDA Takanori; Sato Toshinori
第25回 回路とシステムワークショップ, 31 Jul. 2012

モンテカルロシミュレーションによるソフトエラー率の数量的評価手法
矢野憲; 林田隆則; 佐藤寿倫
電子情報通信学会技術研究報告 VLD2012-21, Vol. 112, No. 114, Jul. 2012

性能や電力とのトレードオフを考慮できる信頼性指標
林田隆則; 安浦寛人; 佐藤寿倫; 小川貢; 吉永亮太; 矢野憲
先進的計算基盤システムシンポジウム, May 2012

GPUを用いた巡回セールスマン問題の並列化解法,
小川哲平; 林田隆則; 佐藤寿倫
2012年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2012

スーパスカラ型CPUコアの低消費電力化手法の提案
柴田善水; 林田隆則; 佐藤寿倫; 高橋伸弥
2012年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2012

分岐予測器の状態数とエントリ数のトレードオフに関する考察
田端隼人; 林田隆則; 佐藤寿倫; 高橋伸弥
2012年電子情報通信学会総合大会ISS特別企画「学生ポスターセッション」, Mar. 2012

タイミングエラー予報フリップフロップを利用したLSI設計におけるチップ面積オーバヘッドの見積もり
吉木崇人; 矢野憲; 林田隆則; 佐藤寿倫
情報処理学会九州支部 火の国情報シンポジウム, Mar. 2012

LSIの信頼性評価指標の提案
林田隆則; 安浦寛人; 矢野憲; 佐藤寿倫
情報処理学会研究報告 ARC, Vol. 2012-ARC-199, No. 6, Mar. 2012

冗長化FF置き換え方式による高信頼性VLSI設計の自動化
矢野 憲; 林田 隆則; 吉木 崇人; 佐藤 寿則
VLD 研究会, Mar. 2012

An Automated Design Approach of Dependable VLSI Using Improved Canary FF
Ken Yano; Takahito Yoshiki; Takanori Hayashida; Toshinori Sato
7th International Workshop on Unique Chips and Systems, Feb. 2012

改良カナリアFFを利用した高信頼性VLSI設計手法の提案
矢野憲; 吉木崇人; 林田隆則; 佐藤寿倫
情報処理学会研究報告 ARC, Vol. 2012-ARC-198, No. 13, Jan. 2012

Hitting Pollack's Law for Improving MPSoC Programmability and Efficiency
Toshinori Sato; Hideki Mori; Rikiya Yano; Takanori Hayashida
3rd Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, 18 Mar. 2011

タイミングエラー予報FF を利用するマルチコアプロセッサのパワーマネージメント
吉木崇人; 佐藤寿倫; 林田隆則
情報処理学会九州支部 火の国情報シンポジウム, 08 Mar. 2011

チップ面積制約下におけるマルチコア化による性能改善要件の調査
小林哲也; 佐藤寿倫; 林田隆則
情報処理学会九州支部 火の国情報シンポジウム, 08 Mar. 2011

構成可変コアによるシングルコア・プロセッサの性能改善検討
矢野力也; 森英貴; 佐藤寿倫; 林田隆則
情報処理学会九州支部 火の国情報シンポジウム, 08 Mar. 2011

A Replacement Strategy for Canary Flip-Flops
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
16th IEEE Pacific Rim International Symposium on Dependable Computing, 15 Dec. 2010

MultiCore Energy Reduction Utilizing Canary FF
Yoshimi Otsuka; Toshinori Sato; Takahito Yoshiki; Takanori Hayashida
10th International Symposium on Communications and Information Technologies, 29 Oct. 2010

ストレス確率を考慮したSRAMの値反転によるNBTI劣化抑制手法
國武勇次; 佐藤寿倫; 安浦寛人
DAシンポジウム, 03 Sep. 2010

A Case Study of Short Term Cell-Flipping Technique for Mitigating NBTI Degradation on Cache
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
2nd Asia Symposium on Quality Electronic Design, 04 Aug. 2010

Signal Probability Control for Relieving NBTI in SRAM Cells
Yuji Kunitake; Toshinori Sato; Hiroto Yasuura
11th International Symposium on Quality Electronic Design, 24 Mar. 2010

Use of Computer Science Unplugged in a renewal Course for a Teacher's License
YOSHIMURA Kenji; TSURUTA Naoyuki; Sato Toshinori
ITK-FUKUOKA2009, 07 Nov. 2009

Computer Science Unpluggedの教員免許更新講習での活用事例
YOSHIMURA Kenji; TSURUTA Naoyuki; Sato Toshinori
IPSJ SIG Technical Report, 10 Oct. 2009

ディペンダブルVLSI設計技術への挑戦
松永裕介; 安浦寛人; 馬場謙介; 吉村正義; 佐藤寿倫; 杉原真
電子情報通信学会2009年総合大会, 17 Mar. 2009

Uncriticality-directed Scheduling for Tackling Variation and Power Challenges
Toshinori Sato; Shingo Watanabe
10th International Symposium on Quality Electronic Design, 16 Mar. 2009

A Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement
Shingo Watanabe; Masanori Hashimoto; Toshinori Sato
10th International Symposium on Quality Electronic Design, 16 Mar. 2009

タイミングエラーの予報を目的とするカナリアFFの挿入位置限定
Yuji Kunitake; Toshinori Sato; Seiichiro Yamaguchi; Hiroto Yasuura
IPSJ SIG Techinical Reports, 2008-SLDM-137-15, 17 Nov. 2008

Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops
Yuji Kunitgake; Toshinori Sato; Hiroto Yasuura
16th IFIP/IEEE International Conference on Very Large Scale Integration, 15 Oct. 2008

Formulating MITF for a Multicore Processor with SEU Tolerance
Toshimasa Funaki; Toshinori Sato
11th Euromicro Conference on Digital System Design, 03 Sep. 2008

Cascading Dependent Operations for Mitigating Timing Variability
Shingo Watanabe; Masanori Hashimoto; Toshinori Sato
Workshop on Quality-Aware Design, 21 Jun. 2008

カナリア方式におけるタイミングエラー見逃しに関する調査
国武勇次; 佐藤寿倫; 安浦寛人
先進的計算基盤システムシンポジウム, 11 Jun. 2008

タイミング歩留まり改善を目的とする演算器カスケーディング
渡辺慎吾; 橋本昌宜; 佐藤寿倫
先進的計算基盤システムシンポジウム, 11 Jun. 2008

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
Tohru Ishihara; Seiichiro Yamaguchi; Yuriko Ishitobi; Tadayuki Matsumura; Yuji Kunitake; Yuichiro Oyama; Yusuke Kaneda; Masanori Muroyama; Toshinori Sato
6th IEEE Symposium on Application Specific Processors, 08 Jun. 2008

入力依存の遅延ばらつきを利用するDVSシステムにおける性能およびエリアオーバーヘッドの改善検討
Yuji kunitake; Toshinori Sato; Hiroto Yasuura
IPSJ SIG Technical Report, 2008-ARC-178, 14 May 2008

Uncriticality-directed Low-power Instruction Scheduling
Shingo Watanabe; Toshinori Sato
IEEE Computer Society Annual Symposium on VLSI, 07 Apr. 2008

Instruction Scheduling for Variation-originated Variable Latencies
Toshinori Sato; Shingo Watanabe
9th International Symposium on Quality Electronic Design, 17 Mar. 2008

性能歩留まり改善を目的とする演算器カスケーディングの提案
Shingo Watanabe; Masanori Hashimoto; Toshinori Sato
情報処理学会研究報告, 2008-ARC-177, Mar. 2008

信頼性と性能のトレードオフ評価指標の提案とそのマルチコアプロセッサへの適用
Toshimasa Funaki; Toshinori Sato
情報処理学会研究報告，2008-ARC-177, Mar. 2008

負荷変動に瞬時適応可能なマルチパフォーマンスプロセッサの設計と評価
Seiichiro Yamaguchi; Yuichiro Oyama; Yuji Kunitake; Tadayuki Matsumura; Yuriko Ishitobi; Masaki Yamaguchi; Donghoon Lee; Yusuke Kaneda; Toshimasa Funaki; Masanori Muroyama; Tohru Ishihara; Toshinori Sato
IPSJ Technical Reports 2008-SLDM-134, Mar. 2008

Dependability, Power, and Performance Trade-Off on a Multicore Processor
Toshinori Sato; Toshimasa Funaki
13th Asia and South Pacific Design Automation Conference, 21 Jan. 2008

ディペンダビリティに配慮する可変レイテンシ演算器のためのスケジューリング方式
Toshinori Sato; Shingo Watanabe
情報処理学会研究報告 2008-ARC-176, Jan. 2008

Power-Performance Trade-Off of a Dependable Multicore Processor
Toshinori Sato; Toshimasa Funaki
13th IEEE Pacific Rim International Symposium on Dependable Computing, 17 Dec. 2007

Dependability-Performance Trade-off on Multiple Clustered Core Processors
Toshimasa Funaki; Toshinori Sato
4th International Workshop on Dependable Embedded Systems, 09 Oct. 2007

性能・消費電力・信頼性の間のトレードオフを考慮出来るマルチ・クラスタ型コア・プロセッサ
Toshinori Sato; Toshimasa Funaki
電子情報通信学会技術研究報告, CPSY2007-31, Oct. 2007

Indirect Tag Search Mechanism for Instruction Window Energy Reduction
Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato
7th International Conference on Computer and Information Technology, Oct. 2007

Critical Issues Regarding A Variation Resilient Flip-Flop
Toshinori Sato; Yuji Kunitake
14th Workshop on Synthesis and System Integration of Mixed Information Technologies, Oct. 2007

Architecture Challenge on SoC Design with Unreliable Transistors
Toshinori Sato
International SoC Design Conference, Oct. 2007

マルチ・クラスタ型コア・プロセッサにおける信頼性と性能のトレードオフ
Toshimasa Funaki; Toshinori Sato
情報処理学会九州支部若手の会セミナー講演論文集, Sep. 2007

命令カスケーディングを利用する耐ばらつきアーキテクチャにおける命令の重要度
Shingo Watanabe; Toshinori Sato
情報処理学会九州支部若手の会セミナー講演論文集, Sep. 2007

Exploiting Input Variations for Energy Reduction
Toshinori Sato; Yuji Kunitake
17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep. 2007

タイミング制約違反を利用する設計手法とコ・シミュレーション環境による評価
Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato
電子情報通信学会技術研究報告, DC2007-11, Aug. 2007

カナリア・フリップフロップを利用するDVS方式の改良
Toshinori Sato; Yuji Kunitake
IPSJ SIG Technical Report, 2007-ARC-171, May 2007

マルチコアプロセッサ向けオンチップキャッシュにおける配線遅延の影響
Yoshitaka Ito; Akihiro Chiyonobu; Toshinori Sato
Symposium on Advanced Computing Systems and Infrastructures, May 2007

カナリア・フリップフロップを利用する省電力マイクロプロセッサの評価
Toshinori Sato
Symposium on Advanced Computing Systems and Infrastructures, May 2007

A Multi-Performance Processor for Low Power Embedded Applications
Yuichiro Oyama; Tohru Ishihara; Toshinori Sato; Hiroto Yasuura
COOL Chips X IEEE Symposium on Low-Power and High-Speed Chips, Apr. 2007

低消費エネルギーシステムのための適応型マルチパフォーマンスプロセッサ
大山裕一郎; 室山真徳; 石原亨; 佐藤寿倫; 安浦寛人
電子情報通信学会 2007年総合大会 ISS特別企画「学生ポスターセッション」, 21 Mar. 2007

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
Toshinori Sato; Yuji Kunitake
8th International Symposium on Quality Electronic Design, Mar. 2007

Challenges in Evaluations for a Typical-Case Design Methodology
Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato
8th International Symposium on Quality Electronic Design, Mar. 2007

省エネルギー指向マルチプロセッサにおける値予測機構の影響
Toshimasa Funaki; Akihiro Chiyonobu; Toshinori Sato
IPSJ SIG Technical Report, 2007-ARC-171, Jan. 2007

キャッシュ非共有型マルチコアプロセッサにおけるキャッシュの性能改善に関する研究
Yoshitaka Ito; Akihiro Chiyonobu; Toshinori Sato
IEICE Technical Report, CPSY2006-51, Dec. 2006

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance
Toshinori Sato; Akihiro Chiyonobu
12th Pacific Rim International Symposium on Dependable Computing, Dec. 2006

省電力に配慮したスケーラブルな命令ウインドウの提案と評価
Shingo Watanabe; Akihiro Chiyonobu; Toshinori Sato
IPSJ SIG Technical Report 2006-ARC-170, Nov. 2006

Improving Energy Efficiency via Speculative Multithreading on MultiCore Processors
Toshinori Sato; Yuu Tanaka; Hidenori Sato; Toshimasa Funaki; Takenori Koushiro; Akihiro Chiyonobu
16th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep. 2006

命令レベル逐次プロセッサ
Toshinori Sato
IPSJ SIG Technical Report, 2006-ARC-169, Aug. 2006

新しいクリティカルパス判定基準を用いたクリティカルパス予測器の評価
Akihiro Chiyonobu; Toshinori Sato
IPSJ SIG Technical Report, 2006-ARC-169, Aug. 2006

タイミング違反を積極的に利用するプロセッサの評価のための回路遅延を考慮するアーキテクチャレベル評価環境の構築
Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato
DA Symposium, Jul. 2006

タイミング違反を利用するマイクロアーキテクチャの演算器における遅延を考慮した評価
Yuji Kunitake; Akihiro Chiyonobu; Koichiro Tanaka; Toshinori Sato
SIG Technical Report (ARC), Jun. 2006

温度を考慮するアーキテクチャの検討のための物理レジスタアクセス頻度の特徴調査
Toshinori Sato; Yuji Kunitake; Akihiro Chiyonobu
SIG Technical Report (ARC), Jun. 2006

省エネルギーな投機的マルチスレッド・マルチコアプロセッサの評価
Toshimasa Funaki; Akihiro Chiyonobu; Toshinori Sato
4th Symposium on Advanced Computing Systems and Infrastructures, May 2006

クリティカルパスを特定するためのヒューリスティックスの改善
Akihiro Chiyonobu; Toshinori Sato
4th Symposium on Advanced Computing Systems and Infrastructures, May 2006

Multiple Clustered Core Processors
Toshinori Sato; Akihiro Chiyonobu
13th Workshop on Synthesis and System Integration of Mixed Information Technologies, Apr. 2006

タイミング違反を利用した省電力プロセッサにおける履歴を用いた性能低下抑制手法
Akihiro Chiyonobu; Kazuhiro Mima; Toshinori Sato
Mitigating Performance Penalty of Constructive Timing Violation Technique, Mar. 2006

A Preliminary Evaluation of Timing-Speculative Instruction Collapsing
Toshinori Sato; Akihiro Chiyonobu
1st Workshop on Introspective Architectures, Feb. 2006

Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors
Toshinori Sato; Akihiro Chiyonobu; Kazuki Joe
9th International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, Jan. 2006

Implementation of a Controller for an FPGA Allowing Dynamic and Partial Reconfiguration on FPGA/DSP Hardware Platform RICE
Takahiro Kawahara; Koichiro Tanaka; Toshinori Sato
International Symposium on Advanced Reconfigurable Systems, Dec. 2005

命令カスケーディングにおける典型的パス遅延の効用
佐藤寿倫; 千代延昭宏
信学技報 CPSY2005-36, Dec. 2005

クリティカルパス情報を利用するキャッシュメモリにおけるデータの重要度に関する調査
藤井誠一郎; 千代延昭宏; 佐藤寿倫
信学技報 CPSY2005-28, Dec. 2005

Energy-Efficient Instruction Scheduling Exploiting Memory Access Slack
Akihiro Chiyonobu; Toshinori Sato
Workshop on Memory Performance: Dealing with Applications, Systems, and Architecture, Sep. 2005

Folding Active List for High Performance and Low Power
Yuichiro Imaizumi; Toshinori Sato
6th International Symposium on High Performance Computing, Sep. 2005

スーパースカラプロセッサにおける命令間依存関係の特徴調査
渡辺慎吾; 千代延昭宏; 佐藤寿倫
第13回電子情報通信学会九州支部学生会講演会, Sep. 2005

スーパースカラプロセッサにおけるレジスタアクセスの特徴調査
国武勇次; 千代延昭宏; 佐藤寿倫
第13回電子情報通信学会九州支部学生会講演会, Sep. 2005

リコンフィギュラブル・システムRICEにおける再構成時間の短縮
川原崇宏; 田中康一郎; 佐藤寿倫
第13回電子情報通信学会九州支部学生会講演会, Sep. 2005

Comparing Fault Recovery Mechanisms for Superscalar Processors
Toshinori Sato
6th International Conference on Dependable Systems and Networks, Jun. 2005

A Preliminary Evaluation on Energy Effciency of a Temperature-aware Multicore-processor
Hidenori Sato; Toshinori Sato
2nd Workshop on Temperature Aware Computer Systems, Jun. 2005

Exploiting Trivial Computation in Dependable Processors
Toshinori Sato
20th International Conference on Computers and Their Applications, Mar. 2005

メモリ内データ圧縮方式を用いたプロセッサ性能改善に関する研究
伊藤義崇; 佐藤寿倫
情報処理学会九州支部若手の会セミナー, Mar. 2005

タイミング違反を利用した省電力ALUにおける違反検出回路の高速化手法とその評価
山原幹雄; 美馬和大; 佐藤寿倫
情報処理学会九州支部 火の国情報シンポジウム, Mar. 2005

スレッドレベル並列性を利用したチップマルチプロセッサの消費電力削減効果
佐藤秀則; 佐藤寿倫; 田中裕
情報処理学会第67回全国大会, Mar. 2005

演算器アレイ型プロセッサへのアプリケーション実装における課題
森下大輔; 佐藤寿倫
情報処理学会第67回全国大会, Mar. 2005

Profiling with Helper Threads
Takamasa Tokunaga; Toshinori Sato
International Conference on Parallel and Distributed Computing and Networks, Feb. 2005

FPGA/CPU混載システムのためのC言語による協調設計環境の実現
田中康一郎; 佐藤寿倫; 有田五次郎
情処研報 2004-SLDM-117-7, Dec. 2004

Exploiting Sub-word Parallelism for Dependable Processors
Toshinori Sato
5th International Conference on Automation & Information, Nov. 2004

Hardware Cost Reduction in Fault Detection Mechanism for Constructive Timing Violation Technique
Kazuhiro Mima; Toshinori Sato
10th International Symposium on Integrated Circuits, Devices and Systems, Sep. 2004

A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion
Akio Kodama; Toshinori Sato
10th International Symposium on Integrated Circuits, Devices and Systems, Sep. 2004

Non-Uniform Set Associative Caches for Power-Aware Embedded Processors
Seiichiro Fujii; Toshinori Sato
International Conference on Embedded and Ubiquitous Computing, Aug. 2004

Exploring Configuration of Dual Speed Pipelines for Criticality-based Energy-efficient Processors
Akihiro Chiyonobu; Toshinori Sato
8th World Multiconference on Systemics, Cybernetics and Informatics, Jul. 2004

The Potential in Energy Efficiency of a Speculative Chip-Multiprocessor
Yuu Tanaka; Toshinori Sato; Takenori Koushiro
16th Symposium on Parallelism in Algorithms and Architectures, Jun. 2004

Investigating Heterogeneous Combination of Functional Units for a Criticality-based Low-power Processor Architecture
Akihiro Chiyonobu; Toshinori Sato
3rd International Symposium on Information and Communication Technologies, Jun. 2004

データの重要度を利用した省電力キャッシュ
藤井誠一郎; 千代延昭宏; 佐藤寿倫
先進的計算基盤システムシンポジウム, May 2004

Leakage Energy Reduction in Register Renaming
Masaharu Goto; Toshinori Sato
1st International Workshop on Embedded Computing Systems, Mar. 2004

A Static and Dynamic Energy Reduction Technique for I-Cache and BTB in Embedded Processors
Hidenori Sato; Toshinori Sato
Asia and South Pacific Design Automation Conference, Jan. 2004

A Field-Customizable and Runtime-Adaptable Microarchitecture
Toshinori Sato; Daisuke Morishita
2nd International Conference on Field-Programmable Technology, Dec. 2003

Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation
Asami Tanino; Toshinori Sato
16th International Conference on Computer Applications in Industry and Engineering, Nov. 2003

Exploiting Instruction Redundancy for Transient Fault Tolerance
Toshinori Sato
18th International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2003

On Identifying Instruction Criticality for Energy-Aware Applications
Akihiro Chiyonobu; Toshinori Sato
12th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2003

A Leakage-Energy-Reduction Technique for High-Associativity Caches in Embedded Systems
Akihito Sakanaka; Toshinori Sato
Workshop on Memory Access Decoupled Architectures and Related Issues, Sep. 2003

Evaluating the Potential of an Energy Reduction Technique Based on Timing Constraint Speculation
Asami Tanino; Toshinori Sato
4th Workshop on Compilers and Operating Systems for Low Power, Sep. 2003

Reducing Static Energy of Cache Memories via Prediction-Table-less Way Prediction
Akihito Sakanaka; Toshinori Sato
13th International Workshop on Power And Timing Modeling, Sep. 2003

SpecC言語向けツールによるハードウェア/ソフトウェア協調設計環境の実現
田中康一郎; 岩谷祐一; 林悠平; 佐藤寿倫; 有田五次郎
DAシンポジウム, Jul. 2003

Simulinkによるハードウェア/ソフトウェア協調設計環境の構築事例
橋本耕太郎; 櫻木誠; 田中康一郎; 佐藤寿倫; 有田五次郎
DAシンポジウム, Jul. 2003

要求適応型IPジェネレータ実現に向けたFPGA向け算術演算器の性能調査
林悠平; 松山正利; 田中康一郎; 佐藤寿倫; 有田 五次郎
DAシンポジウム, Jul. 2003

Design of Hardware/Software Co-Design Emvironment Using SpecC-based Tools
Yuhei Hayashi; Koichiro Tanaka; Toshinori Sato; Itsujiro Arita
International Technical Conference on Circuits/Systems, Computers and Communications, Jul. 2003

An Energy-Efficient Speculative Chip-Multiprocessor Utilizing Trace-level Value Prediction
Takenori Koushiro; Toshinori Sato
1st Value-Prediction Workshop, Jun. 2003

省エネルギー応用におけるプログラムの最長パス特定方法に関する考察
千代延昭宏; 佐藤寿倫; 有田五次郎
先進的計算基盤システムシンポジウム, May 2003

性能ヘテロクラスタにおけるタスク並列処理フレームワークの提案
立川純; 福田健一郎; 平孝則; 大西淑雅; 佐藤寿倫; 有田五次郎
先進的計算基盤システムシンポジウム, May 2003

An Evaluation of Constructive Timing Violation via CSLA Design
Asami Tanino; Toshinori Sato; Itsujiro Arita
6th International Symposium on Low-Power and High-Speed Chips, Apr. 2003

Correlation-based Critical Path Predictors for Low Power Microprocessors
Akihiro Chiyonobu; Toshinori Sato; Itsujiro Arita
6th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Jan. 2003

The KIT COSMOS Processor: A Preliminary Study on Transparent Software Prefetching via Dynamic Optimization
Kou Morita; Toshinori Sato; Itsujiro Arita
6th Workshop on Multi-threaded Execution, Architecture and Compilation, Nov. 2002

計算機クラスタにおける動的スケジューリングを基本とする並列処理環境の検討と提案
立川純; 大西淑雅; 佐藤寿倫; 有田五次郎
コンピュータシステムシンポジウム, Nov. 2002

Reducing Energy Consumption via Low-Cost Value Prediction
Toshinori Sato; Itsujiro Arita
12th International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2002

Simplifying Instruction Issue Logic in Superscalar Processors
Toshinori Sato; Itsujiro Arita
EUROMICRO Symposium on Digital System Design: Architectures, Methods and Tools, Sep. 2002

Design and Implementation of FPGA/DSP Based PCI Card
Koichiro Tanaka; Yuichi Iwaya; Yuhei Hayashi; Toshinori Sato; Itsujiro Arita
Workshop on Logic and Synthesis for Programmable Devices, Aug. 2002

FPGA/DSP混載システムを用いたハードウエア・ソフトウエア設計教育
田中康一郎; 林悠平; 岩谷祐一; 佐藤寿倫; 有田五次郎
DAシンポジウム, Jun. 2002

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization
Toshiyuki Yamamoto; Kou Morita; Toshinori Sato; Itsujiro Arita
International Conference on Parallel and Distributed Processing Techniques and Applications, Jun. 2002

トレースレベル値予測におけるハードウェア量削減方法
神代剛典; 佐藤寿倫; 有田五次郎
並列処理シンポジウム, May 2002

Energy Reduction via Critical Path Prediction
Toshinori Sato; Akihiro Chiyonobu; Itsujiro Arita
Workshop on Complexity-Effective Design, May 2002

Low-Cost Value Predictors Using Frequent Value Locality
Toshinori Sato; Itsujiro Arita
4th International Symposium on High Performance Computing, Jan. 2002

Power and Performance Fitting in Nanometer Design
Toshinori Sato; Takenori Koushiro; Akihiro Chiyonobu; Itujiro Arita
5th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Jan. 2002

Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications
Toshinori Sato; Itsujiro Arita
Pacific Rim International Symposium on Dependable Computing, Dec. 2001

Contrail Processors for Converting High-Performance into Energy-Efficiency
Toshinori Sato; Itsujiro Arita
10th International Conference on Parallel Architectures and Compilation Techniques, Sep. 2001

Constructive Timing Violation for Improving Energy Efficiency
Toshinori Sato; Itsujiro Arita
2nd Workshop on Compilers and Operating Systems for Low Power, Sep. 2001

In Search of Efficient Reliable Processor Design
Toshinori Sato; Itsujiro Arita
30th International Conference on Parallel Processing, Sep. 2001

Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Toshinori Sato; Itsujiro Arita
7th International Euro-Par Conference, Aug. 2001

The KIT COSMOS Processor: Some Ideas on Realizing Complexity-Effective Superscalar Processors
Toshinori Sato; Toshiyuki Yamamoto; Itsujiro Arita
2nd International Conference on Software Engineering, Artificial Intelligence, Networking & Parallel/Distributed Computing, Aug. 2001

Tolerating Transient Faults through an Instruction Reissue Mechanism
Toshinori Sato; Itsujiro Arita
14th International Conference on Parallel and Distributed Computing Systems, Aug. 2001

Transient Faults Tolerance Mechanism for Microprocessors
Toshinori Sato; Itsujiro Arita
2nd International Conference on Dependable Systems and Networks, Jun. 2001

Revisiting Direct Tag Search Algorithm on Superscalar Processors
Toshinori Sato; Yusuke Nakamura; Itsujiro Arita
Workshop on Complexity-Effective Design, Jun. 2001

Influence of Compiler Optimizations on Value Prediction
Toshinori Sato; Akihiko Hamano; Kiichi Sugitani; Itsujiro Arita
9th International Conference on High Performance Computing and Networking Europe, Jun. 2001

クラスタ計算機HYPHENにおけるメモリアクセス機構：HR-net
立川純; 木原大悟; 福澤毅; 田中康一郎; 大西淑雅; Bernady O. Apduhan; 佐藤寿倫; 有田五次郎
並列処理シンポジウム, Jun. 2001

過渡故障に対するマイクロプロセッサ向けフォールトトレランス技術の提案
佐藤寿倫; 有田五次郎
並列処理シンポジウム, Jun. 2001

連想検索を取り除いたスーパースカラプロセッサ向け命令発火機構
佐藤寿倫; 有田五次郎
並列処理シンポジウム, Jun. 2001

Give up Meeting Timing Constraints, but Tolerate Violations
Toshinori Sato; Itsujiro Arita
4th International Symposium on Low-Power and High-Speed Chips, Apr. 2001

The KIT COSMOS Processor: Eliminating Ineffectual Branch Instructions via Concurrent Dynamic Optimization
Toshiyuki Yamamoto; Toshinori Sato; Itsujiro Arita
4th International Symposium on Low-Power and High-Speed Chips, Apr. 2001

Evaluating Effect of Optimization Level on Value Predictability
Kiichi Sugitani; Akihiko Hamano; Toshinori Sato; Itsujiro Arita
4th International Conference on Algorithms and Architectures for Parallel Processing, Dec. 2000

Comprehensive Evaluation of an Instruction Reissue Mechanism
Toshinori Sato; Itsujiro Arita
5th International Symposium on Parallel Architectures, Algorithms and Networks, Dec. 2000

Partial Resolution in Data Value Predictors
Toshinori Sato; Itsujiro Arita
29th International Conference on Parallel Processing, Aug. 2000

計算機クラスタ環境を利用した分散共有メモリ型並列計算機の設計
大濱智宏; 田中康一郎; 佐藤寿倫; 有田五次郎
マルチメディア・分散・協調とモバイルシンポジウム, Jun. 2000

The KIT COSMOS Processor: Introducing CONDOR
Toshinori Sato; Itsujiro Arita
International Conference on Parallel and Distributed Processing Techniques and Applications, Jun. 2000

高性能DSPとCPUによる並列処理環境の設計
林悠平; 田中康一郎; 佐藤寿倫; 有田五次郎
並列処理シンポジウム, May 2000

データ幅を考慮したデータ値予測機構のハードウエア量削減
佐藤寿倫; 有田五次郎
並列処理シンポジウム, May 2000

Table Size Reduction for Data Value Predictors by Exploiting Narrow Width Values
Toshinori Sato; Itsujiro Arita
14th International Conference on Supercomputing, May 2000

300MHz Design Methodology of VU for Emotion Synthesis
Takayuki Kamei; Hideki Takeda; Yukio Ootagro; Takayoshi Shimazawa; Kazuhiko Tachibana; Shinichi Kawakami; Seiji Norimatsu; Fujio Ishihara; Toshinori Sato; Hiroaki Murakami; Nobuhiro Ide; Yukio Endo; Atsushi Kunimatu
Asia and South Pacific Design Automation Conference, Jan. 2000

2.44 GFLOPS 300MHz Floating-Point Vector Processing Unit for High Performance 3D Graphics Computing
Nobuhiro Ide; Masashi Hirano; Yukio Endo; Shin'ichi Yoshioka; Hiroaki Murakami; Atsushi Kunimatsu; Toshinori Sato; Takayuki Kamei; Toyoshi Okada; Masakazu Suzuoki
25th European Solid-State Circuits Conference, Sep. 1999

A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism
Toshinori Sato
EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools, Sep. 1999

Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure
Toshinori Sato
5th International Euro-Par Conference, Aug. 1999

5.5 GFLOPS Vector Units for Emotion Synthesis
Atsushi Kunimatsu; Nobuhiro Ide; Toshinori Sato; Yukio Endo; Hiroaki Murakami; Takayuki Kamei; Masashi Hirano; Masaaki Oka; Akio Ohba; Teiji Yutaka; Toyoshi Okada; Masakazu Suzuoki
Hot Chips 11, Aug. 1999

データ値予測とアドレス予測を組み合わせたデータ投機実行
佐藤寿倫
並列処理シンポジウム, Jun. 1999

Profile-based Selection of Load Value and Address Predictors
Toshinori Sato
nternational Symposium on High Performance Computing, May 1999

Reducing Miss Penalty of Load Value Prediction using Load Address Prediction
Toshinori Sato
4th Australasian Computer Architecture Conference, Jan. 1999

First Step to Combining Control and Data Speculation
Toshinori Sato
2nd International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Oct. 1998

Load Value Prediction using Two-Hop Reference Address Renaming
Toshinori Sato
4th International Conference on Computer Science and Informatics, Oct. 1998

Data Dependence Speculation using Data Address Prediction and its Enhancement with Instruction Reissue
Toshinori Sato
EUROMICRO Conference, Workshop on Digital System Design: Architectures, Methods and Tools, Aug. 1998

Analyzing Overhead of Reissued Instructions on Data Speculative Processors
Toshinori Sato
Workshop on Performance Analysis and its Impact on Design, Jun. 1998

Data Dependence Path Reduction with Tunneling Load Instructions
Toshinori Sato
International Symposium on High Performance Computing, Nov. 1997

Speculative Resolution of Ambiguous Memory Aliasing
Toshinori Sato
1st International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Oct. 1997

NCB: A Mechanism for Improving Instruction Fetching Efficiency
佐藤寿倫
並列処理シンポジウム, May 1997

Evaluation of Architecture-level Power Estimation for CMOS RISC Processors
Toshinori Sato; Yukio Ootaguro; Masato Nagamatsu; Haruyuki Tago
Symposium on Low Power Electronics, Oct. 1995

Power and Performance Simulator:ESP and its Application for 100MIPS/W Class RISC Design
Toshinori Sato; Masato Nagamatsu; Haruyuki Tago
Symposium on Low Power Electronics, Oct. 1994

Automatic Generation of Layout Description for Analog Module Generators
Toshinori Sato; Hidetoshi Onodera; Keikichi Tamaru
International Workshop on Layout Synthesis, May 1992

An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints
Ryousuke Okuda; Toshinori Sato; Hidetoshi Onodera; Keikichi Tamaru
International Conference on Computer-Aided Design, Nov. 1989

システムLSIアーキテクチャ特論
九州大学大学院

システムLSI設計基礎特論
九州大学大学院

計算機工学特論Ⅱ
福岡大学大学院

電子工学実験B
福岡大学

電子通信工学実験
福岡大学

マイクロコンピュータⅡ
福岡大学

ディジタル電子回路
福岡大学

計算機工学Ⅲ
福岡大学

計算機工学Ⅱ
福岡大学

計算機工学Ⅰ
福岡大学

情報システム学特別講義3
電気通信大学大学院

計算機構論
鹿児島大学

実験演習Ⅱ
九州工業大学

実験演習Ⅰ
九州工業大学

基礎実験ⅡA
九州工業大学

人工知能概論
九州工業大学

プロセッサアーキテクチャ特論
九州工業大学大学院

計算機アーキテクチャA
九州工業大学

ディジタルシステム設計
九州工業大学

電子情報工学実験B
福岡大学

電子情報通信学会

情報処理学会

ACM

IEEE

スケーラブルな物理セキュリティを可能にする近似計算の設計基盤と理論の構築
日本学術振興会, 科学研究費, 基盤研究(A)
01 Apr. 2020 - 31 Mar. 2024

階層構造とアクセス方式を同時に改善するメモリシステムの研究
2014 - 2017

近似計算の利用による性能を犠牲にしない省電力な処理方式とその開発を支援する技術
2017

先端記憶デバイスを利用する記憶階層の再構築に関する研究
2011 - 2014

統合的高信頼化設計のためのモデル化と検出・訂正・回復技術
科学技術振興機構
2007 - 2013

ソフトウェアとハードウェアの協調による組込みシステムの消費エネルギー最適化
科学技術振興機構
2006 - 2011

ソフトエラー・ばらつき・経年劣化を考慮可能なプロセッサアーキテクチャの構築
2008 - 2010

価値と信用を搭載するディペンダブルなLSIの設計手法の研究
2008 - 2009

性能と省電力に配慮する高信頼性マルチコアプロセッサに関する研究
栢森情報科学振興財団, 研究助成
2007 - 2007

社会基盤を構築するためのシステムLSI設計手法の研究
2006 - 2006

ユビキタス情報端末向け組込みプロセッサにおけるエネルギー利用効率改善に関する研究
2004 - 2006

履歴に基き再構成するマイクロプロセッサの研究
科学技術振興機構
2001 - 2005

SoC&SiPのためのハイパーネットワーキング技術に関する研究
2003 - 2004

局所的にはクロックに同期し大域的にはクロックを用いないプロセッサに関する研究
2003 - 2004

ユビキタス携帯情報端末応用における組み込みマイクロプロセッサに関する研究
財団法人北田奨学会記念財団, 研究開発助成金
2003 - 2003

高命令レベル並列処理技術を用いるマイクロプロセッサの実現方式に関する研究
2001 - 2003

マイクロプロセッサにおける故障耐性に関する研究
財団法人大川情報通信基金, 研究助成
2001 - 2001

高性能プロセッサアーキテクチャの低消費電力技術への応用に関する研究
株式会社半導体理工学研究センター
2001 - 2001

マイクロプロセッサにおける高命令レベル並列処理のための投機実行方式に関する研究
2000 - 2001

プログラムの動的最適化に基づくプロセッサ高性能化に関する研究
財団法人福岡県産業・科学技術振興財団, テーマ探索・シーズ発掘事業研究助成
2000 - 2000

特許4062095, キャッシュメモリ
佐藤 寿倫

特許3893463, キャッシュメモリ、及びキャッシュメモリの電力削減方法
佐藤 寿倫

特許公開2004-334296, 特許出願2003-125394, 電力制御装置
佐藤 寿倫

USP 6,643,767, Instruction scheduling system of a processor

特許3435267, マイクロプロセッサ及びそのロードアドレス予想方法
佐藤 寿倫

USP 6,516,409, Processor provided with a data value prediction circuit and a branch prediction circuit

USP 6,415,380, Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction

特許公開2001-209535, 特許出願2000-18291, プロセッサの命令スケジューリング装置
佐藤 寿倫

USP 6,119,220, Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions

特許公開2000-132390, プロセッサ及び分岐予測器

特許公開平11-259295, プロセッサの命令スケジューリング装置

特許公開平11-212788, プロセッサのデータ供給装置

USP 5,903,768, Pipelined Microprocessor and load address prediction method therefor

特許公開平10-214188, プロセッサの命令供給方法及び装置

USP 5,754,435, Method and apparatus for calculating power consumption of integrated circuit

特許公開平9-44362, コンパイラ

特許公開平8-44788, 集積回路の消費電力算出方法及びその装置

特許公開平7-191947, 並列計算機

特許公開平6-243116, 並列計算機のプロセッサ間通信制御装置

特許公開平6-68053, 並列計算機