2025年05月
2025 IEEE the 14th International Conference on Communications, Circuits, and Systems (ICCCAS 2025), Best Reviwer Award
Kentaroh Katoh

2024年12月
ICTSS 2024, Best Presentation Award
Physically Unclonable Functions: A Survey and Our Direction
K.Katoh, T. Nakura, and H. Kobayashi

2023年12月
ICTSS 2023, Best Paper Award
A Fine On-Chip Online Delay Measurement Using a MUX Chain for Failure Prediction and Analysis
K. Katoh;T. Nakura, X. Wen, and H. Kobayashi

2022年12月
ICTSS 2022, Best Paper Award
A Physical Unclonable Function Using Time-to-Digital Converter
K. Katoh;S. Yamamoto;Z. Zhao;Y. Zhao;S. Katayama;A. Kuwana;K. Sato;T. Ishida;T. Okamoto;T. Ichikawa;T. Nakatani;K. Hatayama;H. Kobayashi

2015年10月
IEEE 7th International Conference on Information Technology and Electrical Engineering (ICITEE2015), Best Paper Award
Acceleration of Scan-Based On-Chip Delay Measurement Using Extra Latches and Multiple Asynchronous Transfer Scan Chains
K. Kato and S. Choomchuay

A Survey on Physically Unclonable Function: its Basics and Current Progress
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
Journal of Technology and Social Science, 2026年, 査読有り
筆頭著者

A Fine Delay Measurement Using Forward and Backward Phase Shift for Online Failure Prediction and Analysis
Kentaroh Katoh; Toru Nakura; Xiaoqing Wen; Haruo Kobayashi
Journal of Technology and Social Science (JTSS), 2024年07月, 8(1):12 - 22, 査読有り
筆頭著者

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing
Shogo Katayama; Takayuki Nakatani; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi
IEICE Electronics Express, 2023年01月10日, 20(1):20220470 - 20220470, 査読有り

Metallic Ratio Equivalent-Time Sampling and Application to TDC Linearity Calibration
Shuhei Yamamoto; Yuto Sasaki; Yujie Zhao; Anna Kuwana; Kentaroh Katoh; Zheming Zhang; Jianglin Wei; Tri Minh Tran; Shogo Katayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
IEEE Transactions on Device and Materials Reliability, 2022年06月, 22(2):142 - 153, 査読有り

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies
Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Jianglin Wei; Haruo Kobayashi; Takayuki Nakatani; Kazumi Hatayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
Journal of Electronic Testing, 2022年02月, 38(1):21 - 38, 査読有り

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
Kentaro KATO; Somsak CHOOMCHUAY
IEICE Transactions on Information and Systems, 2017年, E100.D(12):2953 - 2961, 査読有り
筆頭著者

Time-to-Digital Converter-Based Maximum Delay Sensor for On-Line Timing Error Detection in Logic Block of Very Large Scale Integration Circuits
Kentaroh Katoh; Kazuteru Namba
Sensors and Materials, 2015年, 27(10):933 - 943, 査読有り
筆頭著者

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator
Kentaroh Katoh; Yutaro Kobayashi; Takeshi Chujo; Junshan Wang; Ensi Li; Congbing Li; Haruo Kobayashi
Journal of Electronic Testing, 2014年11月05日, 30(6):653 - 663, 査読有り

Analog/mixed-signal circuit design in nano CMOS era
Haruo Kobayashi; Hitoshi Aoki; Kentaroh Katoh; Congbing Li
IEICE Electronics Express, 2014年, 11(3):20142001 - 20142001, 査読有り

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection
K. Katoh; K. Namba; H. Ito
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012年05月, 20(5):804 - 817, 査読有り

Area Reduction Techniques for Embedded Delay Measurement Using Signature Registers
加藤 健太郎
鶴岡工業高等専門学校研究紀要,第46号 pp.61～66, 2012年02月, 査読有り

差分によるVLSI回路の遅延測定
田辺融; 加藤健太郎; 難波一輝; 伊藤秀男
電子情報通信学会論文誌 D, Vol.J93-D, No.4, 2010年04月, 93(4):460 - 468, 査読有り

高集積化システムＬＳＩのためのスキャンテスト設計法
加藤 健太郎
千葉大学, 2009年03月
筆頭著者

Design for Delay Fault Testability of 2-Rail Logic Circuits
加藤 健太郎
IEICE Trans. Inf. & Syst., Vol. E92-D, No. 2, 2009年02月, E92D(2):336 - 341, 査読有り
筆頭著者

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH; Kazuteru NAMBA; Hideo ITO
IEICE Transactions on Information and Systems, 2009年, E92-D(3):433 - 442, 査読有り
筆頭著者

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
Information and Media Technologies, 2008年

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
IPSJ Transactions on System LSI Design Methodology, 2008年, 1:91 - 103, 査読有り
筆頭著者

環境との相互作用を用いた自律移動ロボットの識別能力の進化的獲得
加藤 健太郎
名古屋大学, 1997年03月
筆頭著者

Delay Characterization for FPGA PUFs Using Fully Synchronous On-Chip PLL Techniques
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
SWTEST Asia - Semiconductor Wafer Test Conference in Japan 2025, 2025年11月, 査読有り
筆頭著者

High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
2025 IEEE International Test Conference (ITC), 2025年09月20日, :458 - 461, 査読有り
筆頭著者

TDC/ADC PUFの提案（AMD FPGAのためのデュアルTDC測定系を用いたストロングPUF/ コードばらつきを用いたADC PUF）
加藤健太郎; 名倉徹; 小林春夫
第91回FTC研究会, 2025年07月

CMOSロジック素子を用いた組み込み可能なピコ秒オーダ遅延測定技術
加藤健太郎; 小林春夫
ひびきのテスト研究会 第７回会合, 2025年05月
筆頭著者

A Strong Physical Unclonable Function Using Dual Time-to-Digital Converters for AMD FPGAs
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
Proceedings of 2025 IEEE the 14th International Conference on Communications, Circuits, and Systems (ICCCAS 2025), 2025年05月, 査読有り
筆頭著者

A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
2025 Design, Automation & Test in Europe Conference (DATE), 2025年03月31日, :1 - 2
筆頭著者

Physically Unclonable Functions: A Survey and Our Direction
Kentaroh Katoh; Toru Nakura; Haruo Kobayashi
The 8th International Conference on Technology and Social Science (ICTSS 2024)., 2024年12月, 査読有り
筆頭著者

Toward Unification of Digital Error Correction Algorithms for ADCs with Redundancy
Haruo Kobayashi; Tomohiko Ogawa; Yutaro Kobayashi; Kentaroh Katoh; Jiangling Wei
IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, 2024年10月

Renaissance of ADC Testing Fundamentals
Haruo Kobayashi; Keno Sato; Takayuki Nakatani; Shuhei Yamamoto; Anna Kuwana; Yujie Zhao; Jianglin Wei; Kentaroh Katoh
IEEE 6th International Conference on Circuits and Systems, 2024年09月
ラスト(シニア)オーサー

Error Correction and Self-Calibration of Analogue- Digital Mixed-Signal Integrated Circuits
Haruo Kobayashi; Kentatoh Katoh
International Summit on Semiconductors, Optoelectronics and Nanostructures (ISSON2024),, 2024年05月, 査読有り

A Fine On-Chip Online Delay Measurement Using a MUX Chain for Failure Prediction and Analysis
Kentaroh Katoh; Toru Nakura; Xiaoqing Wen; Haruo Kobayashi
the 7th International Conference on Technology and Social Science ICTSS 2023, 2023年12月, 査読有り
筆頭著者

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Keno Sato; Takayuki Nakatani; Takeshi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Daisuke Iimori; Misaki Takagi; Yujie, Zhao; Shuhei Yamamoto; Anna Kuwana; Kentaroh Katoh; Kazumi Hatayama; Kobayashi Haruo
IEEE Int. Test Conf., Oct. 2023, to appaear, 2023年10月, 査読有り

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation
Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
7th IEEE Int. Test Conf. in Asia, Shimane, Japan, Oct. 2023, to appear, 2023年09月, 査読有り
筆頭著者

Inductor ESR Compensation for LC Analog Filters
Misaki Takagi; T. Nakatani; S. Katayama; D. Iimori; G. Ogihara; Y. Zhao; S. Yamamoto; Kobayashi
32nd International Workshop on Post-Binary ULSI Systems (ULSIWS) Matsue, Shimane, Japan, 2023年05月, 査読有り

Design Consideration for LC Analog Filters: Inductor ESR Compensation, Mutual Inductance Effect and Variable Center Frequency
Misaki Takagi; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi
8th International Congress on Information and Communication Technology (ICICT 2023), 2023年02月, 査読有り

SAR Time-to-Digital Converter with 1 ps Resolution for LSI Test System
D. Iimori; T. Nakatani; S. Katayama; M. Takagi; Y. Zhao; A. Kuwana; K. Katoh; K. Hatayama; H. Kobayashi; K. Sato; T. Ishida; T. Okamoto; T. Ichikawa
8th International Congress on Information and Communication Technology (ICICT 2023), 2023年02月, 査読有り

Signal Estimation by Prony's Method for Application to ADC Testing
Siwei Li; Anna Kuwana; Yuki Yanadori; Shogo Katayama; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Takayuki Nakatanii; Kazumi Hatayama; Haruo Kobayashi
2022年12月, 査読有り

Effect of the Delay Elements Variation on Time-to-Digital Converter Linearity
Zhang Zheming; Anna Kuwana; Shogo Katayama; Shuhei Yamamoto; Kentaroh Katoh; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, 2022年12月, 査読有り

Time-to-Digital Converter Linearity Calibration with Metallic Ratio Sampling
Shuhei Yamamoto; Kentaroh Katoh; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the Joint International Conferences of the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, 2022年12月, 査読有り

A Physical Unclonable Function Using Time-to-Digital Converter
Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi
the Joint International Conferences of the 11th International∙Science, Social Sciences, Engineering and Energy Conference I-SEEC 2022, the 6th International Conference on Technology and Social Science ICTSS 2022, 2022年12月, 査読有り
筆頭著者

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST
Keno Sato; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa; Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Kazumi Hatayama; Haruo Kobayashi
2022 IEEE 31st Asian Test Symposium (ATS), 2022年11月, 査読有り

Evaluation of Code Selective Histogram Algorithm For ADC Linearity Test
Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Daisuke Iimori; Yuki Ozawa; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
2022 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2022年10月26日, 査読有り

Challenges for Waveform Sampling and Related Technologies
Haruo Kobayashi; Kentaroh Katoh; Shuhei Yamamoto; Yujie Zhao; Shogo Katayama; Jianglin Wei; Yonglun Yan; Dan Yao; Xueyan Bai; Anna Kuwana
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022年10月25日, 査読有り

Recent Innovation of Waveform Acquisition Methods: Residue Sampling and Metallic Ratio Sampling
Haruo Kobayashi; Anna Kuwana; Shogo Katayama; Shuhei Yamamoto; Yujie Zhao; Kentaroh Katoh; Yonglun Yan; Koji Asami; Masahiro Ishida
11th IEEE International Conference on Communications, Circuits and Systems, 2022年05月, 査読有り

Innovative Practices Track: Innovative Analog Circuit Testing Technologies
Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel Barragan; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; Kazumi Hatayama; Haruo Kobayashi; Keno Sato; Takashi Ishida; Toshiyuki Okamoto; Tamotsu Ichikawa
2022 IEEE 40th VLSI Test Symposium (VTS), 2022年04月25日, 査読有り

Deterministic Path Delay Measurement Using Short Cycle Test Pattern
Kentaro Kato
2017 IEEE 26th Asian Test Symposium (ATS), 2017年11月, 査読有り
筆頭著者

An on-chip delay measurement using adjacency testable scan design
Kentaro Kato; Somsak Choomchuay
2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), 2015年10月, :508 - 513, 査読有り
筆頭著者

Acceleration of scan-based on-chip delay measurement using extra latches and multiple asynchronous transfer scan chains
Kentaro Kato; Somsak Choomchuay
2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), 2015年10月, :514 - 519, 査読有り
筆頭著者

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement
Kentaroh Katoh; Kazuteru Namba
Sixteenth International Symposium on Quality Electronic Design, 2015年03月, 査読有り
筆頭著者

A TDC-Based Online Maximum Delay Analyzer
K. Katoh; K. Namba
International Conference of Global Network for Innovative Technology, 2014年12月, :326 - 329, 査読有り
筆頭著者

Time-to-digital converter architecture with residue arithmetic and its FPGA implementation
Congbing Li; Kentaroh Katoh; Junshan Wang; Shu Wu; Shaiful Nizam Mohyar; Haruo Kobayashi
2014 International SoC Design Conference (ISOCC), 2014年11月, :104 - 105, 査読有り

Experimental verification of timing measurement circuit with self-calibration
Takeshi Chujo; Daiki Hirabayashi; Congbing Li; Yutaro Kobayashi; Junshan Wang; Haruo Kobayashi; Kentaroh Katoh; Sato Koshi
19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings, 2014年09月, 査読有り

Digital Compensation for Timing Mismatches in Interleaved ADCs
Ru Yi; Minghui Wu; Koji Asami; Haruo Kobayashi; Ramin Khatami; Atsuhiro Katayama; Isao Shimizu; Kentaroh Katoh
2013 22nd Asian Test Symposium, 2013年11月, 査読有り

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators
Kentaroh Katoh; Yuta Doi; Satoshi Ito; Haruo Kobayashi; Ensi Li; Nobukazu Takai; Osamu Kobayashi
2013 22nd Asian Test Symposium, 2013年11月, :140 - 146, 査読有り
筆頭著者

Fast Scan-based On-Chip Delay Measurement Using Multiple Asynchronous Transfer Scan Chains
加藤 健太郎
IEEE International Test Conference 2013要旨集, Anaheim, U.S. P012, 2013年10月, 査読有り

バウンダリスキャンと組み込み再構成可能ハードウェアを用いたSOCのオンラインインターコネクトテスト法
加藤 健太郎
電子情報通信学会技術報告,DC-2013-14, pp.25～29, 2013年06月

隣接テスト機構を用いたオンチップ遅延測定法
加藤 健太郎
電子情報通信学会技術報告, DC-2013-8 pp.43-48, 2013年03月

Time-multiplexed on-chip delay measurement for dependable high-speed digital LSIs
Kentaroh Katoh; Kei Itagaki; Shinichiro Hoshina
The 1st IEEE Global Conference on Consumer Electronics 2012, 2012年10月, :726 - 727, 査読有り
筆頭著者

組み込み遅延測定回路を用いた時分割オンチップパス遅延測定のための入力系列データ量削減の１手法
加藤 健太郎
電子情報通信学会技術報告, DC-2012-6 pp.7-13, 2012年06月

半導体集積回路及び半導体集積回路の検査方法（再掲）
加藤 健太郎; 難波一輝; 伊藤秀男
特願2009-265825,特開2011-113984, 2011年11月

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
2010 19th IEEE Asian Test Symposium, 2010年12月, :343 - 348, 査読有り
筆頭著者

A low-area and short-time scan-based embedded delay measurement using signature registers
Kentaroh Katoh; Kazuteru Namba; Hideo Ito
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, 2010年04月, :311 - 314, 査読有り
筆頭著者

半導体集積回路及び半導体集積回路の検査方法(再掲）
加藤健太郎; 難波一輝; 伊藤秀男
特願2007-233346,特開2009-063518, 2009年11月

半導体集積回路(再掲）
加藤健太郎; 難波一輝; 伊藤秀男
特願2007-233388,特開2009-063519, 2009年09月

A Delay Measurement Technique Using Signature Registers
Kentaroh Katoh; Toru Tanabe; Haque Md Zahidul; Kazuteru Namba; Hideo Ito
2009 Asian Test Symposium, 2009年, :157 - 162, 査読有り
筆頭著者

Design for Delay Fault Testing of 2-Rail Logic Circuits
Kentaroh Katoh; Namba Kazuteru; Hideo Ito
Proceedings of Indonessia-Japan Joint Scientific Symposium pp.57-62, 2008年09月, 査読有り
筆頭著者

遅延故障テスト容易化FF方式の下での2段階テストデータ圧縮法
加藤健太郎; 難波一輝; 伊藤秀男
電子情報通信学会技術報告, DC-2007-25, 2007年11月

Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability
Abderrahim Doumar; Kentaroh Katoh; Hideo Ito
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007年09月, 査読有り

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
K. Katoh; H. Ito
Eleventh IEEE European Test Symposium (ETS'06), 2006年05月, :69 - 74, 査読有り
筆頭著者

粗粒度動的再構成可能デバイスのPE部テストのためのDFT
加藤健太郎; 姚玉敏; 難波一輝; 伊藤秀男
電子情報通信学会技術報告, DC-2006-4, 2006年04月

Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift
K. Katoh; A. Doumar; H. Ito
11th IEEE International On-Line Testing Symposium, 2005年, 査読有り

2024年04月 - 現在
情報処理学会

2004年07月 - 現在
米国電気学会

2002年06月 - 現在
電子情報通信学会

AD変換器のデジタル自己校正・誤差補正アルゴリズム統一理論とテスト技術の研究
日本学術振興会, 科学研究費助成事業, 基盤研究(C)
群馬大学
2025年04月01日 - 2028年03月31日

動的命令コード符号化を用いたハッキング検出可能車載向けセキュアプロセッサの開発
日本学術振興会, 科学研究費助成事業, 基盤研究(C)
鶴岡工業高等専門学校
2018年04月01日 - 2021年03月31日

PRAMの書き込み時間削減に適した符号
日本学術振興会, 科学研究費助成事業, 基盤研究(C)
千葉大学
2015年04月01日 - 2018年03月31日