2017年10月
IEEE International Test Conference, 2016 Best Paper Award
Toru Nakura;Naoki Terao;Masahiro Ishida;Rimon Ikeno;Takashi Kusaka;Tetsuya Iizuka;Kunihiro Asada

2017年10月
JETTA/TTTC, 2016 Best Paper Award
Masahiro Ishida;Toru Nakura;Takashi Kusaka;Satoshi Komatsu;Kunihiro Asada
Journal of Electronic Testing: Theory and Application (JETTA), Vol.32, Issue 3, pp.257-271, June 2016.

2015年12月
IP SoC Conference, 2005 Best Paper Award
Toru Nakura;Makoto Ikeda;Kunihiro Asada
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), pp.160-164, Dec. 2005.

2013年05月
電子情報通信学会 平成 24 年度 論文賞 (英文誌 C)
Toru Nakura;Kunihiro Asada
IEICE Trans. on Electronics, Vol.E95-C No.2, pp.297-302, March 2012.

2007年05月
電子情報通信学会 平成 17 年度 論文賞 (英文誌 C)
Toru Nakura;Makoto Ikeda;Kunihiro Asada
IEICE Trans. on Electronics, Vol.E88-C No.5, pp.782-787, May 2005.

2005年05月
第 7 回 LSI IP デザインアワード, IP 最優秀賞
LSI電源用di/dt測定回路コア
名倉 徹;池田 誠;浅田 邦博

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop.
Tetsuya Iizuka; Meikan Chin; Toru Nakura; Kunihiro Asada
IEICE Transactions on Electronics, 2022年10月, 105-C(10):544 - 551

Light Detection and Ranging (LIDAR) Laser Altimeter for the Martian Moons Exploration (MMX) Spacecraft
Hiroki Senshu; Takahide Mizuno; Kazuhiro Umetani; Toru Nakura; Akihi; ro Konishi; Akihiko Ogawa; Hirokazu Ikeda; Koji Matsumoto; Hiromoto Noda; Yoshi; aki Ishihara; Sho Sasaki; Naoki Tateno; Yasuyuki Ikuse; Katsunori Mayuzumi; Hisayoshi Kashine
Springer Earth, Planets and Space, 2021年12月15日, 73(219):1 - 6, 査読有り

Computing-in-Memory Demonstration of Multiple-State(>8) Analog Memory Cell with Ultra-Low(<1nA/cell) Current Enabled by Monolithic CAAC-IGZO FET + Si CMOS FET Stack for Highly-Efficient AI Application
S. Ohshita; H. Rikimaru; K. Tsuda; H. Godo; Y. Kurokawa; Y. Ando; H. Sawai; Y. Yamane; S. Yamazaki; T. Nakura; K.-C. Huang; H. Yoshida; Miller Liao; S.-Z. Chang
International Conference on Solid State Devices and Materials (SSDM), 2021年09月, A-8-01:1 - 2, 査読有り

A Compact Quick-Start Sub-mW Pulse-Width-Controlled PLL with Automated Layout Synthesis using a Place-and-Route Tool
Wang Jing; Tetsuya Iizuka; Zule Xu; Toru Nakura
IEICE Electronics Express, 2019年10月, 16(19):1 - 6, 査読有り

Inverter Using CAAC-IGZO FET with 60-nm Gate Length Fabricated in BEOL
H. Kunitake; T. Koshida; K. Ohshima; K. Tsuda; N. Matsumoto; S. Ohshita; Y. Okazaki; T. Murakawa; T. Atsumi; T. Nakura; K. Kato; S. Yamazaki
International Conference on Solid State Devices and Materials (SSDM), 2019年07月, G-1-03:1 - 2, 査読有り

A 65nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficienty at 10mA Load
Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IFIP AIST 561 VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2019年07月, :1 - 13, 査読有り

A 65nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficienty at 10mA Load
Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IFIP AIST 561 VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2019年07月, 査読有り

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
Tetsuya Iizuka; Kai Xu; Xiao Yang; Toru Nakura; Kunihiro Asada
IEICE Electron. Express, 2019年, 16(19):20190390 - 20190390

Capacitor Insertion Methodology to power Distribution Network for Improving Power Integrity
Shigeaki Hashimoto; Satoshi Komatsu; Toru Nakura
DesignCon, 2019年

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Convertersion
Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
FIP/IEEE/AICA International Conference on Very Large Scale Integration (VLSI-SoC), 2018年10月, :Sess.3 - 3, 査読有り

Analysis and design of impulse signal generator based on current-mode excitation and transmission line resonator
Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
Analog Integrated Circuits and Signal Processing, 2018年06月25日, :1 - 14, 査読有り

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment
Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada
Journal of Electronic Testing: Theory and Applications (JETTA), 2018年04月01日, 34(2):147 - 161

Triangular active charge injection method for resonant power supply noise reduction
Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IEICE Transactions on Electronics, 2018年04月01日, E101C(4):292 - 298

Quick-start Pulse Width Controlled PLL with frequency and phase presetting
Toru Nakura; Tsukasa Kagaya; Tetsuya Iizuka; Kunihiro Asada
IEICE Transactions on Electronics, 2018年04月01日, E101C(4):218 - 223

Time-domain approach for analog circuits in deep sub-micron LSI
Kunihiro Asada; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda
IEICE Electronics Express, 2018年03月25日, 15(6):pp.1 - 21

Optimal design method of sub-ranging ADC based on stochastic comparator
MD. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018年02月01日, E101A(2):410 - 424, 査読有り

Fault Detection of VLSI Power Supply Network based on Current Estimation from Surface Magnetic Field
Daigo Takahashi; Tetsuya Iizuka; Nguyen Ngoc Mai-Khanh; Toru Nakura; Kunihiro Asada
IEEE Trans. on Instrumentation and Measurement, 2018年, 68(7):2519 - 2530, 査読有り

A 16bit 2.0ps Resolution Two-Step TDC in 0.18um CMOS utilizing Pulse-Shrinking Fine Stage with Build-In Coarse Gain Calibration
Ryuichi Enomoto; Testsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada
IEEE Trans. on Very Large Scale Integration Systems,, 2018年, 27(1):11 - 19

A PLL compiler from specification to GDSII
Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2017年12月01日, E100A(12):2741 - 2749, 査読有り

A Triangular Active Charge Injection Scheme using a Resistive Current for Resonant Power Supply Noise Suppression
Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017年12月, :pp.318 - 321

An Ultra-Wide-Range Fine-Resolution Two-Step Time-to-Digital Converter with Bult-In Foreground Coarse Gain Calibration
Ryuichi Enomoto; Tetsuya Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017年12月, :pp.231 - 234

40-kS/s 16-bit Non-Binary SAR ADC in 0.18um CMOS with Noise-Tunable Comparator
Takaaki Ito; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017年12月, :pp.1 - 4

Improvement of Power Integrity with Sub-RDL STO Thin Film Capacitors for WLP/FO-WLP
Masamitsu Yoshizawa; Atsunori Hattori; Hirotaka Hatano; Younggun Han; Osamu Horiuchi; Yoshihisa Katoh; Toru Nakura
IEEE CPMT Symposium Japan (ICSJ), 2017年11月, Sess.13-2:pp.-

A SPAD Array Sensor based on Breakdown Pixel Extraction Architecture with Background Readout for Scintillation Detector
Xiao Yang; Kai Xu; Tetsuya Iizuka; Toru Nakura; Hongbo Zhu; Kunihiro Asada
IEEE Sensors, 2017年10月, :pp.525 - 527

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring
Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2017年09月, E100C(9):736 - 745, 査読有り

Impulse Signal Generator based on Current-Mode Excitation and Transmission Line Resonator
Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEEE New Circuit and System Conference (NEWCAS), 2017年06月, :pp.257 - 260

Extension of Power Supply Impedance Emulation Method on ATE for Multiple Power Domain
Neoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada
IEEE European Test Symposium (ETS), 2017年05月, Sess.P1-4

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR
Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2017年01月, E100A(1):200 - 209, 査読有り

A 15 x 15 SPAD Array Sensor with Breakdown-Pixel-Extraction Architecture for Efficient Data Readout
Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017年, :23 - 24

CMOS-on-Quartz Pulse Generator for Low Power Applications
Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017年, :29 - 30

High spatial resolution detection method for point light source in scintillator
Kai Xu; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IS and T International Symposium on Electronic Imaging Science and Technology, 2017年, :18 - 23

Analysis of VLSI Power Supply Network based on Current Estimation through Magnetic Field Measurement
Yuki Oda; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
2017 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS), 2017年, :pp.327 - 332

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing
Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2016年10月, E99C(10):1219 - 1225, 査読有り

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing
Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2016年06月, 32(3):257 - 271, 査読有り

A 15 x 15 single photon avalanche diode sensor featuring breakdown pixels extraction architecture for efficient data readout
Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
JAPANESE JOURNAL OF APPLIED PHYSICS, 2016年04月, 55(4):04EF04, 査読有り

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors
Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016年03月, 25(3):pp. 1640017-1-1640017-16, 査読有り

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface
Toshiyuki Kikkawa; Toru Nakura; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2016年02月, E99C(2):275 - 284, 査読有り

Analytical Design Optimization of Sub-ranging ADC Based on Stochastic Comparator
Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016年, :517 - 522

Analysis and Design of a Triangular Active Charge Injection for Stabilizing Resonant Power Supply Noise
Masahiro Kano; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016年, :386 - 391

Fully Automated PLL Compiler Generating Final GDS from Specification
Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016年, Sess. 6B:437 - 442

Analysis and Implementation of Quick-Start Pulse Generator by CMOS Flipped on Quartz Substrate
Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
2016 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), 2016年, :3 - 6

One Week TAT of 0.8 mu m CMOS Gate Array with Analog Elements for Educational Exercise
Toru Nakura; Yuki Okamoto; Yoshio Mita; Kunihiro Asada
2016 11TH EUROPEAN WORKSHOP ON MICROELECTRONICS EDUCATION (EWME), 2016年, Sess.6-2

A 4-Cycle-Start-Up Reference-Clock-Less All-Digital Burst-Mode CDR based on Cycle-Lock Gated-Oscillator with Frequency Tracking
Tetsuya Iizuka; Norihito Tohge; Satoshi Miura; Yoshimichi Murakami; Toru Nakura; Kunihiro Asada
ESSCIRC CONFERENCE 2016, 2016年, :301 - 304

A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection utilizing Built-In Offset Pulse
Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada
2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2016年, :313 - 316

Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board
Toru Nakura; Naoki Terao; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada
PROCEEDINGS 2016 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2016年, Sess.14-1

Resonant Power Supply Noise Reduction Using a Triangular Active Charge Injection
Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 2016年, :113 - 116

A CMOS SPAD Sensor Featuring Asynchronous Event-Extraction Readout Architecture for Faint Light Detection
Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
JJAP Solid State Devices and Materials (SSDM), 2015年09月, Sess.F-1-4

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer
Toru Nakura; Masahiro Kano; Masamitsu Yoshizawa; Atsunori Hattori; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2015年07月, E98C(7):734 - 740, 査読有り

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors
Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2015年04月, :pp.131 - 136

Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline
Toru Nakura; Hiroaki Matsui; Kunihiro Asada
IEICE ELECTRONICS EXPRESS, 2015年, 12(3):pp.1 - 8, 査読有り

An on-chip Transfer Function Measurement of PLLs with Triangular Modulated Stimulus
Toshiyuki Kikkawa; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE SIXTH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ASQED 2015, 2015年, :197 - 202

Resonant Power Supply Noise Cancelling with Noise Detector based in DLL and Vernier TDC
Masahiro Kano; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE SIXTH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ASQED 2015, 2015年, :192 - 196

Non-Linearity Analysis of Stochastic Time-to-Digital Converter
Val Mikos; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE SIXTH ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ASQED 2015, 2015年, :171 - 176

Tracking PVT variations of Pulse Width Controlled PLL using Variable-Length Ring Oscillator
Takashi Toi; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
2015 NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP & INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC), 2015年, :pp.1 - 4

Improvement of Power Integrity with Die-Attached STO Thin Film Capacitors
Masamitsu Yoshizawa; Seisei Oyamada; Atsunori Hattori; Toru Nakura; Masahiro Kano; Kunihiro Asada
IEEE CPMT SYMPOSIUM JAPAN 2015, (ICSJ 2015), 2015年, :183 - 186

A Calibration-Free Time Difference Accumulator Using Two Pulses Propagating on a Single Buffer Ring
Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2015年, :145 - 148

A Technique for Analyzing On-chip Power Supply Impedance
Masahiro Ishida; Toru Nakura; Akira Matsukawa; Rimon Ikeno; Kunihiro Asada
2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 2015年, :193 - 198

High-speed and Lowleakage Characteristics of 60-nm C-axis Aligned Crystalline Oxide Semiconductor FET with GHz-ordered Cutoff Frequency
Y. Yakubo; S. Nagatsuka; S. Matsuda; S. Hondo; Y. Hata; Y. Okazaki; Y. Yamamoto; M. Nagai; M. Sakakura; T. Nakura; Y. Yamamoto; S. Yamazaki
JJAP Solid State Devices and Materials (SSDM), 2014年09月, Sess.E-7-1

Burst-Pulse Generator Based on Transmission Line Toward Sub-MMW
Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2014年, :59 - 64

Numerical and Theoretical Analysis on Voltage and Time Domain Dynamic Range of scaled CMOS Circuits.
Kevin Ngari Muriithi; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2014年, :282 - 285

Streaming Distribution of a Live Seminar: Rudimentary Knowledge for LSI Design
Toru Nakura; Kunihiro Asada
10TH EUROPEAN WORKSHOP ON MICROELECTRONICS EDUCATION (EWME), 2014年, Sess.4-1:133 - 136

Improvement of Power Integrity with Thin Film Capacitors Embedded in Organic Interposer
Masamitsu Yoshizawa; Seisei Oyamada; Atsunori Hattori; Toru Nakura; Kunihiro Asada
2014 IEEE CPMT SYMPOSIUM JAPAN (ICSJ), 2014年, No,53:122 - 125

Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills
Masahiro Ishida; Takashi Kusaka; Toru Nakura; Satoshi Komatsu; Kunihiro Asada
2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014年, Sess.8-2

Improvement of Power Integrity with Thin Film Capacitors Embedded in Organic Interposer
Masamitsu Yoshizawa; Seisei Oyamada; Atsunori Hattori; Toru Nakura; Kunihiro Asada
2014 IEEE CPMT SYMPOSIUM JAPAN (ICSJ), 2014年, Sess.11-3:122 - 125

Resonant Power Supply Noise Reduction using On-Die Decoupling Capacitors Embedded in Organic Interposer
Toru Nakura; Masahiro Kano; Masamitsu Yoshizawa; Seisei Oyamada; Atsunori Hattori; Kunihiro Asada
2014 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING & SYSTEMS SYMPOSIUM (EDAPS), 2014年, Sess. M-III.7:93 - 96

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Jinmyoung Kim; Toru Nakura; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2013年04月, E96C(4):560 - 567, 査読有り

An All-Digital Time Difference Hold-and-Replication Circuit utilizing a Dual Pulse Ring Oscillator
Tetsuya Iizuka; Teruki Someya; Toru Nakura; Kunihiro Asada
2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013年, Sess.M-1

Pulse Width Controlled PLL/DLL using Soft Thermometer Code
Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013年, :345 - 348

Low Pass Filter-less Pulse Width Controlled PLL with Zero Phase Offset Using Pulse Width Accumulator
Tomohiko Yano; Toru Nakura; Kunihiro Asada
2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2013年, :625 - 628

A Pulse Width controlled PLL and its automated design flow
Norihito Tohge; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2013年, :5 - 8

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme
Kazutoshi Kodama; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2012年12月, E95C(12):1857 - 1863, 査読有り

Review and Future Prospects on Time-Domain Analog Approach
Kunihiro Asada; Toru Nakura; Tetsuya Iizuka
The second Solid-State Systems Symposium 2012 (4S-2012), 2012年08月, Sess.2

Intelligent-PAD2.0: Platform for On-line SoC Health Condition Monitoring
Makoto Ikeda; Tetsuya Iizuka; Satoshi Komatsu; Masahiro. Sasaki; Toru Nakura; Kunihiro Asada
European Workshop on Microelectronics Education (EWME 2012), 2012年05月, Grenoble

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2012年04月, E95C(4):643 - 650, 査読有り

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
Toru Nakura; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2012年02月, E95C(2):297 - 302, 査読有り

7.5Vmax Arbitrary Waveform Generator with 65nm Standard CMOS under 1.2V Supply Voltage
Toru Nakura; Yoshio Mita; Tetsuya Iizuka; Kunihiro Asada
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012年, M-05

Impact of all-digital PLL on SoC testing
Toru Nakura; Tetsuya Iizuka; Kunihiro Asada
Proceedings of the Asian Test Symposium, 2012年, Sess7B:252 - 257

Power Integrity Control of ATE for Emulating Power Supply Fluctuations on Customer Environment
Masahiro Ishida; Toru Nakura; Toshiyuki Kikkawa; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada
PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012, 2012年, :Paper 7.3

Stress-Balance Flip-Flops for NBTI Tolerant Circuit based on Fine-Grain Redundancy
Teruki Nakasato; Toru Nakura; Kunihiro Asada
International SoC Conference (ISOCC), 2011年11月, :pp.150 - 153

1.0 Ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2011年06月, E94C(6):1098 - 1104, 査読有り

Cascaded Time Difference Amplifier with Differential Logic Delay Cell
Shingo Mandai; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2011年04月, E94C(4):654 - 662, 査読有り

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2011年04月, E94C(4):487 - 494, 査読有り

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2011年04月, E94C(4):511 - 519, 査読有り

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter
Jaehyun Jeong; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011年, :pp.79 - 80

Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), 2011年, :111 - 114

An automatic phase control circuit with DLL-like architecture for phased array antenna systems
Toshiyuki Kikkawa; Toru Nakura; Kunihiro Asada
Proceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011, 2011年, B1.1:25 - 28

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
European Solid-State Circuits Conference, 2011年, :183 - 186

Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement
Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), 2010年11月, - Poster 2

A 8bit two stage time-to-digital converter using time difference amplifier
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE ELECTRONICS EXPRESS, 2010年07月, 7(13):943 - 948, 査読有り

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
Benjamin Stefan Devlin; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2010年07月, E93A(7):1319 - 1328, 査読有り

Time Difference Amplifier with Robust Gain Using Closed-Loop Control
Toru Nakura; Shingo Mandai; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2010年03月, E93C(3):303 - 308, 査読有り

Cascaded Time Difference Amplifier using Differential Logic Delay Cell
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010年, :350 - +

Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability and Aging Effects
Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010年, :167 - 172

A 8bit Two Stage Time-to-Digital Converter Using 16x Cascaded Time Difference Amplifier in 0.18um CMOS
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
MELECON 2010: THE 15TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, 2010年, :280 - 285

Resonant Supply Noise Canceller utilizing Parasitic Capacitance of Sleep Blocks
Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada
2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2010年, :119 - +

A 8bit Two Stage Time-to-Digital Converter Using 16x Cascaded Time Difference Amplifier in 0.18um CMOS
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
MELECON 2010: THE 15TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, 2010年, vol.7(no.13):280 - 285, 査読有り

A toggle-type peak hold circuit for local power supply noise detection
Yuki Tamaki; Toru Nakura; Makoto Ikeda; Kunihiro Asada
Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010, 2010年, :29 - 32

Time-to-digital converter based on time difference amplifier with non-linearity calibration
Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada
ESSCIRC 2010 - 36th European Solid State Circuits Conference, 2010年, :266 - 269

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter
Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada
ESSCIRC 2010 - 36th European Solid State Circuits Conference, 2010年, :182 - 185

A robust pulse delay circuit utilizing a differential buffer ring
Jaehyun Jeong; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2010 International SoC Design Conference, ISOCC 2010, 2010年, :272 - 275

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2009年06月, E92C(6):798 - 805, 査読有り

Ultra High Speed 3-D Image Sensor
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
International Image Sensor Workshop (IISW), 2009年06月, Sess.8-3

Cascaded Time Difference Amplifier using Differential Logic Delay Cell
Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009年, :194 - +, 査読有り

Moebius Circuit: Dual-Rail Dynamic Logic for Logic Gate Level Pipeline with Error Gate Search Feature
MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009年, :177 - 180

All Digital Baseband 50 Mbps Data Recovery Using 5x Oversampling With 0.9 Data Unit Interval Clock Jitter Tolerance
Sanad Bushnaq; Toru Nakura; Makoto Ikeda; Kunihiro Asada
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2009年, :206 - +

Measurement of Power Supply Noise Tolerance of Self-timed Processor
Kunihiro Asada; Taku Sogabe; Toru Nakura; Makoto Ikeda
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2009年, :128 - +

Time Difference Amplifier using Closed-Loop Gain Control
Toru Nakura; Shingo Mandai; Makoto Ikeda; Kunihiro Asada
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009年, sess.20-2:208 - +

SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
Toru Nakura; Yutaro Tatemura; Goerschwin Fey; Makoto Ikeda; Satoshi Komatsu; Kunihiro Asada
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2, 2009年, :643 - +

647 MHz, 0.642pJ/block/cycle 65nm Self Synchronous FPGA
Benjamin Devlin; Jeong MyeongGyu; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2009 PROCEEDINGS OF ESSCIRC, 2009年, :157 - +

All Digital Wireless Transceiver Using Modified BPSK and 2/3 Sub-sampling Technique
Sanad Bushnaq; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009年, :469 - +

Ring Oscillator Based Random Number Generator Utilizing Wake-up Time Uncertainty
Toru Nakura; Makoto Ikeda; Kunihiro Asada
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2009年, :121 - 124

Throughput optimization by pipeline alignment of a self synchronous FPGA
Benjamin Devlin; Toru Nakura; Makoto Ikeda; Kunihiro Asada
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, 2009年, :312 - 315

Variation Tolerant Transceiver Design For System-on-Glass
JinMyong Kim; Toru Nakura; Makoto Ikeda; Kunihiro Asada
European Solid-State Circuits Conference (ESSCIRC), 2008年09月, :Poster

Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip
Shingo Mandai; Taihei Monma; Toru Nakura; Makoto Ikeda; Kunihiro Asada
ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008年, :89 - +

Design of active substrate noise canceller using power suplly di/dt detector
Taisuke Kazama; Toru Nakura; Makoto Ikeda; Kunihiro Asada
PROCEEDINGS OF THE ASP-DAC 2007, 2007年, :100 - +, 査読有り

Design of Active Substrate Noise Canceller using Power Line di/dt Detector
Taisuke Kazama; Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEEE Asia and South Pacific Deasign Automation Conference (ASP-DAC), 2007年01月, Sess.1D-5:pp.100 - 102

LAGS system using data/instruction grain power control
Makoto Ikeda; Taku Sogabe; Ken Ishii; Masayuki Mizuno; Toru Nakura; Koichi Nose; Kunihiro Asada
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2007年, :61 - 587

Fine-grain redundant logic using defect-prediction flip-flops
Toru Nakura; Koichi Nose; Masayuki Mizuno
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2007年, :397 - 611

Autonomous di/dt control of power supply for margin aware operation
Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2006年11月, E89C(11):1689 - 1694, 査読有り

Feedforward active substrate noise cancelling based on di/dt of power supply
T Nakura; M Ikeda; K Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2006年03月, E89C(3):364 - 369, 査読有り

Optimization of active substrate noise cancelling technique using power line di/dt detector
Taisuke Kazama; Toru Nakura; Makoto Ikeda; Kunihiro Asada
2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, 2006年, Sess.8-3:239 - 242

On-chip di/dt Detector IP for Power Supply
Toru Nakura; Makoto Ikeda; Kunihiro Asada
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), 2005年12月, :pp.160 - 164

On-chip di/dt detector circuit
T Nakura; M Ikeda; K Asada
IEICE TRANSACTIONS ON ELECTRONICS, 2005年05月, E88C(5):782 - 787, 査読有り

Preliminary experiments for power supply noise reduction using on-board stubs
Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE Transactions on Electronics, 2005年, E88-C(8):1734 - 1739, 査読有り

Feedforward active substrate noise cancelling technique using power supply di/dt detector
T Nakura; M Ikeda; K Asada
2005 Symposium on VLSI Circuits, Digest of Technical Papers, 2005年, Sess.18-4:284 - 287

Stub vs. Capacitor for power supply noise reduction
Toru Nakura; Makoto Ikeda; Kunihiro Asada
IEICE Transactions on Electronics, 2005年, E88-C(1):125 - 131, 査読有り

Autonomous di/dt noise control scheme for margin aware operation
T Nakura; M Ikeda; K Asada
ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2005年, Sess.8.G.2:467 - 470

A Study on Power Line Noise Reduction in Large Scale Integration
Toru Nakura; Superviser; Kunihiro Asada
2005年

Power supply di/dt measurement using on-chip di/dt detector circuit
T Nakura; M Ikeda; K Asada
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004年, Sess.7-4:106 - 109

On-chip di/dt detector circuit for power supply line
T Nakura; M Ikeda; K Asada
ICMTS 2004: PROCEEDINGS OF THE 2004 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2004年, Sess.1-4:19 - 22

Design and measurement of on-chip di/dt detector circuit for power supply line
T Nakura; M Ikeda; K Asada
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004年, Sess.16-12:426 - 427

Preliminary experiments for power supply noise reduction using stubs
T Nakura; M Ikeda; K Asada
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004年, Sess.13-7:286 - 289

Preliminary experiments for power supply noise reduction using stubs
T Nakura; M Ikeda; K Asada
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004年, Vol.E88-C(No.8):286 - 289, 査読有り

Theoretical study of stubs for power line noise reduction
T Nakura; M Ikeda; K Asada
PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003年, Sess.31-4:715 - 718

A 3.6-Gb/s 340-mW 16 : 1 pipe-lined multiplexer using 0.18 mu m SOI-CMOS technology
T Nakura; K Ueda; K Kubo; Y Matsuda; K Mashiko; T Yoshihara
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000年05月, 35(5):751 - 756, 査読有り

LAPAREX - An automatic parameter extraction program for gain- and index-coupled distributed feedback semiconductor lasers, and its application to observation of changing coupling coefficients with currents
T Nakura; Y Nakano
IEICE TRANSACTIONS ON ELECTRONICS, 2000年03月, E83C(3):488 - 495, 査読有り

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology
Toru Nakura; Kimio Ueda; Kazuo Kubo; Yoshio Matsuda; Koichiro Mashiko; Tsutomu Yoshihara
IEEE Journal of Solid-State Circuits, 2000年, 35(5):751 - 756

A 1.8 V 2.5 GHz PLL using 0.18 μm SOI/CMOS technology
K. Yoshimura; Kimio Ueda; Toru Nakura; K. Kubo; Koichiro Mashiko; K. S. Maeda; Shigeru Maegawa; Y. Yamaguchi; Yoshio Matsuda
IEEE SOI Conference, 1999年10月, :pp.12 - 13

A 2.0Gbps multiplexer and a 2.7Gbps demultiplexer using 0.35μm SOI-CMOS technology
K. Ueda; T. Nakura; Y. Wada; S. Maeda; K. Mashiko
European Solid-State Circuits Conference, 1998年, :448 - 451

First observation of changing coupling coefficients in a gain-coupled DFB laser with absorptive grating by automatic parameter extraction from subthreshold spectra
Toru Nakura; Kenji Sato; Masaki Funabashi; Geert Morthier; Roel Baets; Yoshiaki Nakano; Kunio Tada
APS/IEEE/OSA Conference on Lasers and Electro-Optics (CLEO'97), 1997年05月, CThM1:pp.136 - 136

Comparision of InGaAs absorptive grating structures in 1.55 μm InGaAsP/InP strained MQW gain-coupled DFB lasers
Masaki Funabashi; H. Kawanishi; Tsurugi K. Sudoh; Toru Nakura; D. Schmitz; F. Schulte; Yoshiaki Nakano; Kunio Tada
IEEE International Conference on Indium Phosphide and Related Materials, 1997年, Sess.11-15:292 - 295

Characterization of excess noise induced by external reflection in 1.55 mu m gain-coupled DFB lasers of absorptive grating type
Y Nakano; M Funabashi; R Yatsu; T Nakura; K Tada
IOOC-ECOC 97 - 11TH INTERNATIONAL CONFERENCE ON INTEGRATED OPTICS AND OPTICAL FIBRE COMMUNICATIONS / 23RD EUROPEAN CONFERENCE ON OPTICAL COMMUNICATIONS, VOL 1, 1997年, Sess.22-25(448):25 - 28

Essential Knowledge for Transistor Level LSI Circuit Design
Toru Nakura
Springer, 2016年06月

LSI設計常識講座
名倉 徹
東京大学出版会, 2011年12月

アナログRF CMOS集積回路設計 応用編
STARC教育推進室監修; 浅田邦博; 松澤昭共編; 著者:名倉 徹; 飯塚哲也; 池田誠; 岡田健一; 倉科隆; 佐々木昌浩; 藤島実; 松澤昭, 第12章「PLLとシンセサイザ」pp.279-307, 第13章「VGA」pp.308-318, 第22章「トランシーバ測定」pp.464-486)
培風館, 2011年02月

火星衛星探査計画 MMX LIDAR 開発状況報告 2
千秋 博紀; 水野 貴秀; 名倉 徹; 梅谷 和弘; 小西 晃央; 松本 晃治; 野田 寛大; 舘野 直樹; 生瀬 裕之; 黛克典; 加瀬 貞二; 樫根 久佳
火星衛星探査計画 MMX LIDAR 開発状況報告 2, 2021年11月

火星衛星探査計画 MMX LIDAR 開発状況報告
千秋 博紀; 水野 貴秀; 小西 晃央; 梅谷 和弘; 名倉 徹; 松本 晃治; 野田 寛大; 生瀬 裕之; 黛克典; 加瀬 貞二; 樫根 久佳
宇宙科学技術連合講演会, 2020年10月

火星衛星探査機(MMX)用レーザ高度計(LIDAR)の部分試作評価
生瀬 裕之; 黛 克典; 加瀬 貞二; 川原 章裕; 千秋 博紀; 水野 貴秀; 小西 晃央; 梅谷 和弘; 名倉 徹
宇宙科学技術連合講演会, 2019年11月

集積回路の動作信頼性とパワーインテグリティ
名倉 徹
村田製作所 講演, 2019年11月

集積回路の作り方
名倉 徹
JAXA 談話会, 2019年10月

ランドサイド・コンデンサ挿入によるパワーインテグリティ向上解析手法
橋本 樹明; 小松 聡; 名倉 徹
Synopsys Users Group Japan (SNUG), 2019年09月

自動配置配線を用いた高速起動パルス幅制御PLL回路の設計と性能比較
王 環; 飯塚 哲也; 飯塚 哲也; 名倉 徹
電子情報通信学会 総合大会, 2019年03月

Power Supply Noise Suppression and Emulation to Improve Reliability of LSI Operations
Toru Nakura
IEEE International Conference on Microelectronics Test Structures (ICMTS), 2019年03月

HSPICE を用いた PLL 仕様からレイアウトまでの完全自動合成
名倉 徹
Synopsys Users Group Japan (SNUG), 2018年06月, 日本シノプシス

遅延制御バッファにより周波数追従範囲を拡大した高速起動完全デジタルCDR回路の設計
陳 明翰; 飯塚 哲也; 名倉 徹; 浅田 邦博
電子情報通信学会 集積回路研究会, 2017年12月

ノイズ可変比較器を用いたノンバイナリ逐次比較型アナログ-デジタル変換器の設計
伊藤 貴亮; 飯塚 哲也; 名倉 徹; 浅田 邦博
電子情報通信学会 集積回路研究会, 2017年12月

統計的コンパレータを用いたレベルクロス検出手法の性能解析
杉山 泰基; 飯塚 哲也; 山口 隆弘; 名倉 徹; 浅田 邦博
電子情報通信学会 集積回路研究会, 2017年12月

US2017/0220060, Power Supply Apparatus
Toru Nakura, Masahiro Ishida, Takashi Kusaka, Rimon Ikeno, Naoki Terao, Kunihiro Asada

US2017/0214513A1, Clock Generating Apparatus and Clock Data Recoverying Apparatus

US9702902, Test Apparatus
Toru Nakura, Satoshi Komatsu, Masahiro Ishida, Kunihiro Asada

US9287852, PCT/JP2012/063206, Signal Conversion Circuit, PLL Circuit, Delay Adjustment Circuit, and Phase Control Circuit
Toru Nakura, Kunihiro Asada

特開2017-134649, 電源装置およびそれを用いた試験装置、電源電圧の供給方法
名倉 徹, 石田 雅裕, 日下 崇, 池野 理門, 浅田 邦博, 寺尾 直樹

特開2017-130838, クロック生成装置およびクロックデータ復元装置
飯塚 哲也, 名倉 徹, 峠 仁人, 浅田 邦博, 三浦 賢, 村上 芳道

特開2017-1300730, 時間デジタル変換方法および時間-デジタル変換装置
飯塚 哲也, 古賀 丈尚, 名倉 徹, 浅田 邦博

特開2015-115618, 位相同期ループ回路及び発振方法
名倉 徹, 矢野 智比古, 浅田 邦博

特開2014-215145, 光子検出装置および放射線測定装置
名倉 徹, 浅田 邦博, 飯塚 哲也, 久保田 透

特開2014-074622, 試験装置および試験条件の取得方法
名倉 徹, 石田 雅裕, 小松 聡, 浅田 邦博

US7908538, Failure Prediction Circuit and Method, and Semiconductor Integrated Circuit
Toru Nakura, Masayuki Mizuno, Koichi Nose

US6477186, Fast operating multiplexer
Toru Nakura, Kmio Ueda

US6472712, Semiconductor device with reduced transistor leakage current
Toru Nakura, Kmio Ueda

US6249157, Synchronous frequency dividing circuit
Toru Nakura, Kmio Ueda

US6208494, Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing varous types of surge
Toru Nakura, Kmio Ueda

6101233, Counter circuit
Toru Nakura, Kmio Ueda

特開2000-012788, 半導体集積回路装置
名倉 徹, 上田 公大

特開平11-330951, カウンタ回路
名倉 徹, 上田 公大